Qadeer A. Qureshi

Person

Dripping Springs, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Hardware-based memory initialization
- Patent number 9,595,350
- Issue date Mar 14, 2017
- NXP USA, INC.
- Henning F. Spruth
- G11 - INFORMATION STORAGE
Information Patent Grant
Content addressable memory with search line test circuitry
- Patent number 9,418,741
- Issue date Aug 16, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Ravindraraj Ramaraju
- G11 - INFORMATION STORAGE
Information Patent Grant
Memories having a built-in self-test (BIST) feature
- Patent number 9,384,856
- Issue date Jul 5, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Henning F. Spruth
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic voltage adjustment for memory
- Patent number 7,616,509
- Issue date Nov 10, 2009
- FREESCALE SEMICONDUCTOR, INC.
- Qadeer A. Qureshi
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method for adjusting an operating parameter of an int...
- Patent number 7,483,327
- Issue date Jan 27, 2009
- FREESCALE SEMICONDUCTOR, INC.
- Qadeer A. Qureshi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory with fault tolerant reference circuitry
- Patent number 7,444,557
- Issue date Oct 28, 2008
- FREESCALE SEMICONDUCTOR, INC.
- Alexander B. Hoefler
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit fuses having corresponding storage circuitry
- Patent number 7,362,645
- Issue date Apr 22, 2008
- FREESCALE SEMICONDUCTOR, INC.
- Qadeer A. Qureshi
- G11 - INFORMATION STORAGE
Information Patent Grant
Temperature based DRAM refresh
- Patent number 7,295,484
- Issue date Nov 13, 2007
- FREESCALE SEMICONDUCTOR, INC.
- Arnaldo R. Cruz
- G11 - INFORMATION STORAGE
Information Patent Grant
Nonvolatile memory system using magneto-resistive random access mem...
- Patent number 7,245,527
- Issue date Jul 17, 2007
- FREESCALE SEMICONDUCTOR, INC.
- Qadeer A. Qureshi
- G11 - INFORMATION STORAGE
Information Patent Grant
Temperature based DRAM refresh
- Patent number 7,206,244
- Issue date Apr 17, 2007
- FREESCALE SEMICONDUCTOR, INC.
- Arnaldo R. Cruz
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit power management for reducing leakage current in...
- Patent number 6,917,555
- Issue date Jul 12, 2005
- FREESCALE SEMICONDUCTOR, INC.
- Ryan D. Bedwell
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MEMORY SYSTEM WITH REDUNDANT OPERATION
- Publication number 20220277800
- Publication date Sep 1, 2022
- NXP USA, Inc.
- Rodrigo Pascoal Zeli
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORIES HAVING A BUILT-IN SELF-TEST (BIST) FEATURE
- Publication number 20150162098
- Publication date Jun 11, 2015
- HENNING F. SPRUTH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE-BASED MEMORY INITIALIZATION
- Publication number 20140129883
- Publication date May 8, 2014
- FREESCALE SEMICONDUCTOR, INC.
- Henning F. Spruth
- G01 - MEASURING TESTING
Information Patent Application
DYNAMIC VOLTAGE ADJUSTMENT FOR MEMORY
- Publication number 20090016140
- Publication date Jan 15, 2009
- Qadeer A. Qureshi
- G11 - INFORMATION STORAGE
Information Patent Application
TEMPERATURE BASED DRAM REFRESH
- Publication number 20070153606
- Publication date Jul 5, 2007
- FREESCALE SEMICONDUCTOR, INC.
- Arnaldo R. Cruz
- G11 - INFORMATION STORAGE
Information Patent Application
Nonvolatile memory system using magneto-resistive random access mem...
- Publication number 20060256610
- Publication date Nov 16, 2006
- FREESCALE SEMICONDUCTOR, INC.
- Qadeer A. Qureshi
- G11 - INFORMATION STORAGE
Information Patent Application
Temperature based DRAM refresh
- Publication number 20060114734
- Publication date Jun 1, 2006
- Arnaldo R. Cruz
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated circuit fuses having corresponding storage circuitry
- Publication number 20060085702
- Publication date Apr 20, 2006
- Qadeer A. Qureshi
- G11 - INFORMATION STORAGE
Information Patent Application
Memory with fault tolerant reference circuitry
- Publication number 20060039215
- Publication date Feb 23, 2006
- Alexander B. Hoefler
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated circuit power management for reducing leakage current in...
- Publication number 20050068799
- Publication date Mar 31, 2005
- Ryan D. Bedwell
- G06 - COMPUTING CALCULATING COUNTING

Qadeer A. Qureshi

Person

Patents Grantslast 30 patents

Hardware-based memory initialization

Content addressable memory with search line test circuitry

Memories having a built-in self-test (BIST) feature

Dynamic voltage adjustment for memory

Apparatus and method for adjusting an operating parameter of an int...

Memory with fault tolerant reference circuitry

Integrated circuit fuses having corresponding storage circuitry

Temperature based DRAM refresh

Nonvolatile memory system using magneto-resistive random access mem...

Temperature based DRAM refresh

Integrated circuit power management for reducing leakage current in...

Patents Applicationslast 30 patents

MEMORY SYSTEM WITH REDUNDANT OPERATION

MEMORIES HAVING A BUILT-IN SELF-TEST (BIST) FEATURE

HARDWARE-BASED MEMORY INITIALIZATION

DYNAMIC VOLTAGE ADJUSTMENT FOR MEMORY

TEMPERATURE BASED DRAM REFRESH

Nonvolatile memory system using magneto-resistive random access mem...

Temperature based DRAM refresh

Integrated circuit fuses having corresponding storage circuitry

Memory with fault tolerant reference circuitry

Integrated circuit power management for reducing leakage current in...