Qiang Chen

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Sollentuna, SE

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Patents Grantslast 30 patents

Information Patent Grant
Method and layout of semiconductor device with reduced parasitics
- Patent number 8,492,229
- Issue date Jul 23, 2013
- Albert Birner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and layout of semiconductor device with reduced parasitics
- Patent number 8,035,140
- Issue date Oct 11, 2011
- Infineon Technologies AG
- Albert Birner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and layout of semiconductor device with reduced parasitics
- Patent number 7,928,481
- Issue date Apr 19, 2011
- Infineon Technologies AG
- Albert Birner
Information Patent Grant
Integrated circuit ESD protection
- Patent number 7,719,025
- Issue date May 18, 2010
- Infineon Technologies AG
- Qiang Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
LDMOS transistor
- Patent number 7,049,669
- Issue date May 23, 2006
- Infineon Technologies AG
- Gordon Ma
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Method and Layout of Semiconductor Device with Reduced Parasitics
- Publication number 20110294273
- Publication date Dec 1, 2011
- Albert Birner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and Layout of Semiconductor Device with Reduced Parasitics
- Publication number 20090026539
- Publication date Jan 29, 2009
- Albert Birner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated Circuit ESD Protection
- Publication number 20080093624
- Publication date Apr 24, 2008
- Qiang Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LDMOS transistor
- Publication number 20050056889
- Publication date Mar 17, 2005
- Gordon Ma
- H01 - BASIC ELECTRIC ELEMENTS