QIANLI DI

Person

Beijing, CN

People

Patents Grantslast 30 patents

Information Patent Grant
Processor cache with independent pipeline to expedite prefetch request
- Patent number 10,713,172
- Issue date Jul 14, 2020
- SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
- Qianli Di
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method of reducing processor pipeline stall caused by fu...
- Patent number 10,437,599
- Issue date Oct 8, 2019
- SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
- Qianli Di
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method of speculative parallel execution of cache line u...
- Patent number 10,310,859
- Issue date Jun 4, 2019
- VIA ALLIANCE SEMICONDUCTOR CO., LTD.
- Qianli Di
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallelized multiple dispatch system and method for ordered queue...
- Patent number 10,140,128
- Issue date Nov 27, 2018
- VIA ALLIANCE SEMICONDUCTOR CO., LTD.
- Qianli Di
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microprocessor with a reservation stations structure including prim...
- Patent number 9,928,070
- Issue date Mar 27, 2018
- VIA ALLIANCE SEMICONDUCTOR CO., LTD.
- Qianli Di
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SYSTEM AND METHOD OF REDUCING PROCESSOR PIPELINE STALL CAUSED BY FU...
- Publication number 20180307492
- Publication date Oct 25, 2018
- Shanghai Zhaoxin Semiconductor Co., Ltd.
- Qianli DI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR CACHE WITH INDEPENDENT PIPELINE TO EXPEDITE PREFETCH REQUEST
- Publication number 20180307608
- Publication date Oct 25, 2018
- Shanghai Zhaoxin Semiconductor Co., Ltd.
- Qianli DI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD OF EXECUTING CACHE LINE UNALIGNED LOAD INSTRUCTIONS
- Publication number 20180300134
- Publication date Oct 18, 2018
- Shanghai Zhaoxin Semiconductor Co., Ltd.
- Qianli DI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD OF SPECULATIVE PARALLEL EXECUTION OF CACHE LINE U...
- Publication number 20170139718
- Publication date May 18, 2017
- VIA Alliance Semiconductor Co., Ltd.
- QIANLI DI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MICROPROCESSOR WITH FUSED RESERVATION STATIONS STRUCTURE
- Publication number 20170090934
- Publication date Mar 30, 2017
- VIA Alliance Semiconductor Co., Ltd.
- QIANLI DI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD TO REDUCE LOAD-STORE COLLISION PENALTY IN SPECULA...
- Publication number 20160328237
- Publication date Nov 10, 2016
- VIA Alliance Semiconductor Co., Ltd.
- QIANLI DI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARALLELIZED MULTIPLE DISPATCH SYSTEM AND METHOD FOR ORDERED QUEUE...
- Publication number 20160259648
- Publication date Sep 8, 2016
- VIA Alliance Semiconductor Co., Ltd.
- QIANLI DI
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Processor cache with independent pipeline to expedite prefetch request

System and method of reducing processor pipeline stall caused by fu...

System and method of speculative parallel execution of cache line u...

Parallelized multiple dispatch system and method for ordered queue...

Microprocessor with a reservation stations structure including prim...

Patents Applicationslast 30 patents

SYSTEM AND METHOD OF REDUCING PROCESSOR PIPELINE STALL CAUSED BY FU...

PROCESSOR CACHE WITH INDEPENDENT PIPELINE TO EXPEDITE PREFETCH REQUEST

SYSTEM AND METHOD OF EXECUTING CACHE LINE UNALIGNED LOAD INSTRUCTIONS

SYSTEM AND METHOD OF SPECULATIVE PARALLEL EXECUTION OF CACHE LINE U...

MICROPROCESSOR WITH FUSED RESERVATION STATIONS STRUCTURE

SYSTEM AND METHOD TO REDUCE LOAD-STORE COLLISION PENALTY IN SPECULA...

PARALLELIZED MULTIPLE DISPATCH SYSTEM AND METHOD FOR ORDERED QUEUE...