Qiong J. Yu

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San Jose, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Method and system for checking for power errors in ASIC designs
- Patent number 6,829,754
- Issue date Dec 7, 2004
- LSI Logic Corporation
- Qiong J. Yu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of datapath cell placement for bitwise and non-bitwise integ...
- Patent number 6,560,761
- Issue date May 6, 2003
- LSI Logic Corporation
- Qiong J. Yu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of datapath cell placement for an integrated circuit
- Patent number 6,496,967
- Issue date Dec 17, 2002
- LSI Logic Corporation
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING