Quan Shi

Person

Beaverton, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Multi version library cell handling and integrated circuit structur...
- Patent number 12,067,338
- Issue date Aug 20, 2024
- Intel Corporation
- Ranjith Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit structure with front side signal lines and backs...
- Patent number 12,051,692
- Issue date Jul 30, 2024
- Intel Corporation
- Quan Shi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi version library cell handling and integrated circuit structur...
- Patent number 11,271,010
- Issue date Mar 8, 2022
- Intel Corporation
- Ranjith Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and shadow circuits with output joining circuit
- Patent number 7,278,074
- Issue date Oct 2, 2007
- Intel Corporation
- Subhasish Mitra
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
CELL ROWS WITH MIXED HEIGHTS AND MIXED NANORIBBON WIDTHS
- Publication number 20250006721
- Publication date Jan 2, 2025
- Intel Corporation
- Sukru Yemenicioglu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STAGGERED VIA ARCHITECTURE ACROSS UNIT CELLS
- Publication number 20240429161
- Publication date Dec 26, 2024
- Intel Corporation
- Sukru Yemenicioglu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI VERSION LIBRARY CELL HANDLING AND INTEGRATED CIRCUIT STRUCTUR...
- Publication number 20240362391
- Publication date Oct 31, 2024
- Intel Corporation
- Ranjith KUMAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT STRUCTURE WITH FRONT SIDE SIGNAL LINES AND BACKS...
- Publication number 20240355819
- Publication date Oct 24, 2024
- Intel Corporation
- Quan SHI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIELECTRIC BARRIER FOR BACKSIDE INTERCONNECT SEPARATION
- Publication number 20240204064
- Publication date Jun 20, 2024
- Intel Corporation
- Guillaume Bouche
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
High Density Transistor and Routing Track Architecture
- Publication number 20240202415
- Publication date Jun 20, 2024
- Intel Corporation
- Quan Shi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STACKED SOURCE OR DRAIN CONTACT FLYOVER
- Publication number 20240113177
- Publication date Apr 4, 2024
- Intel Corporation
- Sukru Yemenicioglu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOWER DEVICE ACCESS IN STACKED TRANSISTOR DEVICES
- Publication number 20230420460
- Publication date Dec 28, 2023
- Intel Corporation
- Cheng-Ying Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURE WITH FRONT SIDE SIGNAL LINES AND BACKS...
- Publication number 20220262791
- Publication date Aug 18, 2022
- Intel Corporation
- Quan SHI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI VERSION LIBRARY CELL HANDLING AND INTEGRATED CIRCUIT STRUCTUR...
- Publication number 20220149075
- Publication date May 12, 2022
- Intel Corporation
- Ranjith KUMAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI VERSION LIBRARY CELL HANDLING AND INTEGRATED CIRCUIT STRUCTUR...
- Publication number 20200357823
- Publication date Nov 12, 2020
- Intel Corporation
- Ranjith KUMAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and shadow circuits with output joining circuit
- Publication number 20060168489
- Publication date Jul 27, 2006
- Intel Corporation
- Subhasish Mitra
- G01 - MEASURING TESTING

Person

Patents Grantslast 30 patents

Multi version library cell handling and integrated circuit structur...

Integrated circuit structure with front side signal lines and backs...

Multi version library cell handling and integrated circuit structur...

System and shadow circuits with output joining circuit

Patents Applicationslast 30 patents

CELL ROWS WITH MIXED HEIGHTS AND MIXED NANORIBBON WIDTHS

STAGGERED VIA ARCHITECTURE ACROSS UNIT CELLS

MULTI VERSION LIBRARY CELL HANDLING AND INTEGRATED CIRCUIT STRUCTUR...

INTEGRATED CIRCUIT STRUCTURE WITH FRONT SIDE SIGNAL LINES AND BACKS...

DIELECTRIC BARRIER FOR BACKSIDE INTERCONNECT SEPARATION

High Density Transistor and Routing Track Architecture

STACKED SOURCE OR DRAIN CONTACT FLYOVER

LOWER DEVICE ACCESS IN STACKED TRANSISTOR DEVICES

INTEGRATED CIRCUIT STRUCTURE WITH FRONT SIDE SIGNAL LINES AND BACKS...

MULTI VERSION LIBRARY CELL HANDLING AND INTEGRATED CIRCUIT STRUCTUR...

MULTI VERSION LIBRARY CELL HANDLING AND INTEGRATED CIRCUIT STRUCTUR...

System and shadow circuits with output joining circuit