Quinn W. MERRELL

Person

Phoenix, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Parallel deflate decoding method and apparatus
- Patent number 9,697,899
- Issue date Jul 4, 2017
- Intel Corporation
- Lokpraveen B. Mosur
- G11 - INFORMATION STORAGE
Information Patent Grant
Parallel apparatus for high-speed, highly compressed LZ77 tokenizat...
- Patent number 8,766,827
- Issue date Jul 1, 2014
- Intel Corporation
- Andrew Milne
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Compression producing output exhibiting compression ratio that is a...
- Patent number 8,373,583
- Issue date Feb 12, 2013
- Intel Corporation
- Lokpraveen B. Mosur
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for providing a low power mode for a processor...
- Patent number 7,694,080
- Issue date Apr 6, 2010
- Intel Corporation
- Quinn W. Merrell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microprocessor design support for computer system and platform vali...
- Patent number 7,487,398
- Issue date Feb 3, 2009
- Intel Corporation
- Ayman G. Abdo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism handling race conditions in FRC-enabled processors
- Patent number 7,194,671
- Issue date Mar 20, 2007
- Intel Corporation
- Steven J. Tu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transfer of cache lines on-chip between processing cores in a multi...
- Patent number 7,120,755
- Issue date Oct 10, 2006
- Intel Corporation
- Sujat Jamil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microprocessor design support for computer system and platform vali...
- Patent number 7,032,134
- Issue date Apr 18, 2006
- Intel Corporation
- Ayman G. Abdo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for scalable disambiguated coherence in shared...
- Patent number 7,003,632
- Issue date Feb 21, 2006
- Intel Corporation
- Sujat Jamil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for scalable disambiguated coherence in shared...
- Patent number 6,651,145
- Issue date Nov 18, 2003
- Intel Corporation
- Sujat Jamil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Backward inquiry to lower level caches prior to the eviction of a m...
- Patent number 5,829,038
- Issue date Oct 27, 1998
- Intel Corporation
- Quinn Merrell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for exclusively writing tag during write allocate...
- Patent number 5,787,469
- Issue date Jul 28, 1998
- Intel Corporation
- Quinn W. Merrell
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
PARALLEL DEFLATE DECODING METHOD AND APPARATUS
- Publication number 20170178729
- Publication date Jun 22, 2017
- Intel Corporation
- Lokpraveen B. MOSUR
- G11 - INFORMATION STORAGE
Information Patent Application
COMPRESSION PRODUCING OUTPUT EXHIBITING COMPRESSION RATIO THAT IS A...
- Publication number 20120262312
- Publication date Oct 18, 2012
- Lokpraveen B. Mosur
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method and apparatus for providing a low power mode for a processor...
- Publication number 20060143409
- Publication date Jun 29, 2006
- Quinn W. Merrell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dirty line hint array for cache flushing
- Publication number 20060143397
- Publication date Jun 29, 2006
- R. Frank O'Bleness
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Microprocessor design support for computer system and platform vali...
- Publication number 20060107120
- Publication date May 18, 2006
- Intel Corporation
- Ayman G. Abdo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and apparatus for detecting an address conflict
- Publication number 20040153611
- Publication date Aug 5, 2004
- Sujat Jamil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for scalable disambiguated coherence in shared...
- Publication number 20030233523
- Publication date Dec 18, 2003
- Sujat Jamil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Transfer of cache lines on-chip between processing cores in a multi...
- Publication number 20030126365
- Publication date Jul 3, 2003
- Sujat Jamil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanism handling race conditions in FRC-enabled processors
- Publication number 20030126142
- Publication date Jul 3, 2003
- Steven J. Tu
- G06 - COMPUTING CALCULATING COUNTING

Quinn W. MERRELL

Person

Patents Grantslast 30 patents

Parallel deflate decoding method and apparatus

Parallel apparatus for high-speed, highly compressed LZ77 tokenizat...

Compression producing output exhibiting compression ratio that is a...

Method and apparatus for providing a low power mode for a processor...

Microprocessor design support for computer system and platform vali...

Mechanism handling race conditions in FRC-enabled processors

Transfer of cache lines on-chip between processing cores in a multi...

Microprocessor design support for computer system and platform vali...

Method and apparatus for scalable disambiguated coherence in shared...

Method and apparatus for scalable disambiguated coherence in shared...

Backward inquiry to lower level caches prior to the eviction of a m...

System and method for exclusively writing tag during write allocate...

Patents Applicationslast 30 patents

PARALLEL DEFLATE DECODING METHOD AND APPARATUS

COMPRESSION PRODUCING OUTPUT EXHIBITING COMPRESSION RATIO THAT IS A...

Method and apparatus for providing a low power mode for a processor...

Dirty line hint array for cache flushing

Microprocessor design support for computer system and platform vali...

Methods and apparatus for detecting an address conflict

Method and apparatus for scalable disambiguated coherence in shared...

Transfer of cache lines on-chip between processing cores in a multi...

Mechanism handling race conditions in FRC-enabled processors