Rafael C. Camarota

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Unified programmable computational memory and configuration network
- Patent number 11,201,623
- Issue date Dec 14, 2021
- Xilinx, Inc.
- Rafael C. Camarota
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-rank high bandwidth memory (HBM) memory
- Patent number 11,189,338
- Issue date Nov 30, 2021
- Xilinx, Inc.
- Rafael C. Camarota
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Configuring programmable logic region via programmable network
- Patent number 11,169,822
- Issue date Nov 9, 2021
- Xilinx, Inc.
- Rafael C. Camarota
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrating rows of input/output blocks with memory controllers in...
- Patent number 10,963,411
- Issue date Mar 30, 2021
- Xilinx, Inc.
- Martin L. Voogel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layered boundary interconnect
- Patent number 10,929,331
- Issue date Feb 23, 2021
- Xilinx, Inc.
- Rafael C. Camarota
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Standalone interface for stacked silicon interconnect (SSI) technol...
- Patent number 10,784,121
- Issue date Sep 22, 2020
- Xilinx, Inc.
- Rafael C. Camarota
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Boundary logic interface
- Patent number 10,763,862
- Issue date Sep 1, 2020
- Xilinx, Inc.
- Rafael C. Camarota
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Unified programmable computational memory and configuration network
- Patent number 10,673,440
- Issue date Jun 2, 2020
- Xilinx, Inc.
- Rafael C. Camarota
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Auto address generation for switch network
- Patent number 10,621,132
- Issue date Apr 14, 2020
- Xilinx, Inc.
- Rafael C. Camarota
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test network for a network on a chip and a configuration network
- Patent number 10,502,785
- Issue date Dec 10, 2019
- Xilinx, Inc.
- Rafael C. Camarota
- G01 - MEASURING TESTING
Information Patent Grant
Heterogeneous ball pattern package
- Patent number 10,177,107
- Issue date Jan 8, 2019
- Xilinx, Inc.
- Rafael C. Camarota
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Circuit for and method of implementing a scan chain in programmable...
- Patent number 10,069,497
- Issue date Sep 4, 2018
- Xilinx, Inc.
- Benjamin S. Devlin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High bandwidth memory (HBM) bandwidth aggregation switch
- Patent number 9,911,465
- Issue date Mar 6, 2018
- Xilinx, Inc.
- Rafael C. Camarota
- G11 - INFORMATION STORAGE
Information Patent Grant
Rotated integrated circuit die and chip packages having the same
- Patent number 9,882,562
- Issue date Jan 30, 2018
- Xilinx, Inc.
- Martin L. Voogel
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Monolithic integrated circuit die having modular die regions stitch...
- Patent number 9,547,034
- Issue date Jan 17, 2017
- Xilinx, Inc.
- Rafael C. Camarota
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multi-use package substrate
- Patent number 9,204,542
- Issue date Dec 1, 2015
- Xilinx, Inc.
- Tien-Yu Lee
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Memory matrix
- Patent number 9,083,340
- Issue date Jul 14, 2015
- Xilinx, Inc.
- Ephrem C. Wu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Flexible sized die for use in multi-die integrated circuit
- Patent number 9,026,872
- Issue date May 5, 2015
- Xilinx, Inc.
- Rafael C. Camarota
- G01 - MEASURING TESTING
Information Patent Grant
Dual port memory cell
- Patent number 8,913,455
- Issue date Dec 16, 2014
- Xilinx, Inc.
- Rafael C. Camarota
- G11 - INFORMATION STORAGE
Information Patent Grant
Oversized interposer formed from a multi-pattern region mask
- Patent number 8,869,088
- Issue date Oct 21, 2014
- Xilinx, Inc.
- Rafael C. Camarota
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Predicting performance of an integrated circuit
- Patent number 8,712,718
- Issue date Apr 29, 2014
- Xilinx, Inc.
- Rafael C. Camarota
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for self-annealing multi-die interconnect redu...
- Patent number 8,539,420
- Issue date Sep 17, 2013
- Xilinx, Inc.
- Rafael C. Camarota
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Non-disruptive randomly addressable memory system
- Patent number 5,805,503
- Issue date Sep 8, 1998
- Atmel Corporation
- Rafael C. Camarota
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Non-disruptive, randomly addressable memory system
- Patent number 5,488,582
- Issue date Jan 30, 1996
- Atmel Corporation
- Rafael C. Camarota
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High performance output buffer with reduced ground bounce
- Patent number 5,341,040
- Issue date Aug 23, 1994
- National Semiconductor Corporation
- Tim Garverick
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Configuration features in a configurable logic array
- Patent number 5,336,950
- Issue date Aug 9, 1994
- National Semiconductor Corporation
- Sanjay Popli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Power up detect circuit for configurable logic array
- Patent number 5,319,255
- Issue date Jun 7, 1994
- National Semiconductor Corporation
- Tim Garverick
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dynamic three-state bussing capability in a configurable logic array
- Patent number 5,317,209
- Issue date May 31, 1994
- National Semiconductor Corporation
- Tim Garverick
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Versatile and efficient cell-to-local bus interface in a configurab...
- Patent number 5,298,805
- Issue date Mar 29, 1994
- National Semiconductor Corporation
- Tim Garverick
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Versatile programmable logic cell for use in configurable logic arrays
- Patent number 5,245,227
- Issue date Sep 14, 1993
- Atmel Corporation
- Frederick C. Furtek
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
UNIFIED PROGRAMMABLE COMPUTATIONAL MEMORY AND CONFIGURATION NETWORK
- Publication number 20210050853
- Publication date Feb 18, 2021
- Xilinx, Inc.
- Rafael C. Camarota
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BOUNDARY LOGIC INTERFACE
- Publication number 20200274536
- Publication date Aug 27, 2020
- Xilinx, Inc.
- Rafael C. Camarota
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURING PROGRAMMABLE LOGIC REGION VIA PROGRAMMABLE NETWORK
- Publication number 20200264901
- Publication date Aug 20, 2020
- Xilinx, Inc.
- Rafael C. Camarota
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STANDALONE INTERFACE FOR STACKED SILICON INTERCONNECT (SSI) TECHNOL...
- Publication number 20180047663
- Publication date Feb 15, 2018
- Xilinx, Inc.
- Rafael C. Camarota
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HETEROGENEOUS BALL PATTERN PACKAGE
- Publication number 20180033753
- Publication date Feb 1, 2018
- Xilinx, Inc.
- Rafael C. Camarota
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CIRCUIT FOR AND METHOD OF IMPLEMENTING A SCAN CHAIN IN PROGRAMMABLE...
- Publication number 20170373692
- Publication date Dec 28, 2017
- Xilinx, Inc.
- Benjamin S. Devlin
- G01 - MEASURING TESTING
Information Patent Application
MONOLITHIC INTEGRATED CIRCUIT DIE HAVING MODULAR DIE REGIONS STITCH...
- Publication number 20150008954
- Publication date Jan 8, 2015
- Xilinx, Inc.
- Rafael C. Camarota
- G01 - MEASURING TESTING
Information Patent Application
FLEXIBLE SIZED DIE FOR USE IN MULTI-DIE INTEGRATED CIRCUIT
- Publication number 20140049932
- Publication date Feb 20, 2014
- Xilinx, Inc.
- Rafael C. Camarota
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND APPARATUS FOR SELF-ANNEALING MULTI-DIE INTERCONNECT REDU...
- Publication number 20130009694
- Publication date Jan 10, 2013
- Xilinx, Inc.
- Rafael C. Camarota
- H01 - BASIC ELECTRIC ELEMENTS

Rafael C. Camarota

Person

Patents Grantslast 30 patents

Unified programmable computational memory and configuration network

Multi-rank high bandwidth memory (HBM) memory

Configuring programmable logic region via programmable network

Integrating rows of input/output blocks with memory controllers in...

Layered boundary interconnect

Standalone interface for stacked silicon interconnect (SSI) technol...

Boundary logic interface

Unified programmable computational memory and configuration network

Auto address generation for switch network

Test network for a network on a chip and a configuration network

Heterogeneous ball pattern package

Circuit for and method of implementing a scan chain in programmable...

High bandwidth memory (HBM) bandwidth aggregation switch

Rotated integrated circuit die and chip packages having the same

Monolithic integrated circuit die having modular die regions stitch...

Multi-use package substrate

Memory matrix

Flexible sized die for use in multi-die integrated circuit

Dual port memory cell

Oversized interposer formed from a multi-pattern region mask

Predicting performance of an integrated circuit

Method and apparatus for self-annealing multi-die interconnect redu...

Non-disruptive randomly addressable memory system

Non-disruptive, randomly addressable memory system

High performance output buffer with reduced ground bounce

Configuration features in a configurable logic array

Power up detect circuit for configurable logic array

Dynamic three-state bussing capability in a configurable logic array

Versatile and efficient cell-to-local bus interface in a configurab...

Versatile programmable logic cell for use in configurable logic arrays

Patents Applicationslast 30 patents

UNIFIED PROGRAMMABLE COMPUTATIONAL MEMORY AND CONFIGURATION NETWORK

BOUNDARY LOGIC INTERFACE

CONFIGURING PROGRAMMABLE LOGIC REGION VIA PROGRAMMABLE NETWORK

STANDALONE INTERFACE FOR STACKED SILICON INTERCONNECT (SSI) TECHNOL...

HETEROGENEOUS BALL PATTERN PACKAGE

CIRCUIT FOR AND METHOD OF IMPLEMENTING A SCAN CHAIN IN PROGRAMMABLE...

MONOLITHIC INTEGRATED CIRCUIT DIE HAVING MODULAR DIE REGIONS STITCH...

FLEXIBLE SIZED DIE FOR USE IN MULTI-DIE INTEGRATED CIRCUIT

METHOD AND APPARATUS FOR SELF-ANNEALING MULTI-DIE INTERCONNECT REDU...