Raghu G. GopalaKrishnaSetty

Person

Bangalore, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Operating pulsed latches on a variable power supply
- Patent number 11,112,854
- Issue date Sep 7, 2021
- International Business Machines Corporation
- Steven M. Douskey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamically power noise adaptive automatic test pattern generation
- Patent number 10,816,599
- Issue date Oct 27, 2020
- International Business Machines Corporation
- Steven M. Douskey
- G01 - MEASURING TESTING
Information Patent Grant
Logic built in self test circuitry for use in an integrated circuit...
- Patent number 10,746,794
- Issue date Aug 18, 2020
- International Business Machines Corporation
- Satya R. S. Bhamidipati
- G01 - MEASURING TESTING
Information Patent Grant
Logic built in self test circuitry for use in an integrated circuit...
- Patent number 10,739,401
- Issue date Aug 11, 2020
- International Business Machines Corporation
- Satya R. S. Bhamidipati
- G01 - MEASURING TESTING
Information Patent Grant
Logic built in self test circuitry for use in an integrated circuit...
- Patent number 10,649,028
- Issue date May 12, 2020
- International Business Machines Corporation
- Satya R. S. Bhamidipati
- G01 - MEASURING TESTING
Information Patent Grant
Circuit structures to resolve random testability
- Patent number 10,545,190
- Issue date Jan 28, 2020
- International Business Machines Corporation
- Raghu G. GopalaKrishnaSetty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit structures to resolve random testability
- Patent number 10,527,674
- Issue date Jan 7, 2020
- International Business Machines Corporation
- Raghu G. GopalaKrishnaSetty
- G01 - MEASURING TESTING
Information Patent Grant
Self-moderating bus arbitration architecture
- Patent number 10,521,381
- Issue date Dec 31, 2019
- International Business Machines Corporation
- Raghu G. GopalaKrishnaSetty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Operating pulsed latches on a variable power supply
- Patent number 10,386,912
- Issue date Aug 20, 2019
- International Business Machines Corporation
- Steven M. Douskey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Self-moderating bus arbitration architecture
- Patent number 10,303,631
- Issue date May 28, 2019
- International Business Machines Corporation
- Raghu G. GopalaKrishnaSetty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adjusting scan connections based on scan control locations
- Patent number 10,216,885
- Issue date Feb 26, 2019
- International Business Machines Corporation
- Raghu G. GopalaKrishnaSetty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logic built in self test circuitry for use in an integrated circuit...
- Patent number 10,088,524
- Issue date Oct 2, 2018
- International Business Machines Corporation
- Satya R. S. Bhamidipati
- G01 - MEASURING TESTING
Information Patent Grant
Adjusting latency in a scan cell
- Patent number 10,060,971
- Issue date Aug 28, 2018
- International Business Machines Corporation
- Steven M. Douskey
- G01 - MEASURING TESTING
Information Patent Grant
Adjusting latency in a scan cell
- Patent number 10,001,523
- Issue date Jun 19, 2018
- International Business Machines Corporation
- Steven M. Douskey
- G01 - MEASURING TESTING
Information Patent Grant
Adjusting scan connections based on scan control locations
- Patent number 9,934,348
- Issue date Apr 3, 2018
- International Business Machines Corporation
- Raghu G. GopalaKrishnaSetty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Control test point for timing stability during scan capture
- Patent number 9,322,876
- Issue date Apr 26, 2016
- International Business Machines Corporation
- Purushotam Bheemanna
- G01 - MEASURING TESTING
Information Patent Grant
Automatic test pattern generation (ATPG) considering crosstalk effects
- Patent number 9,218,447
- Issue date Dec 22, 2015
- International Business Machines Corporation
- Kanad Basu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Control test point for timing stability during scan capture
- Patent number 9,194,915
- Issue date Nov 24, 2015
- International Business Machines Corporation
- Purushotam Bheemanna
- G01 - MEASURING TESTING
Information Patent Grant
Q-gating cell architecture to satiate the launch-off-shift (LOS) te...
- Patent number 9,086,458
- Issue date Jul 21, 2015
- International Business Machines Corporation
- Raghu G. GopalaKrishnaSetty
- G01 - MEASURING TESTING
Information Patent Grant
Algorithm to identify best Q-gating candidates and a Q-gating cell...
- Patent number 8,898,604
- Issue date Nov 25, 2014
- International Business Machines Corporation
- Raghu G. GopalaKrishnaSetty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay defect testing of power drop effects in integrated circuits
- Patent number 8,776,006
- Issue date Jul 8, 2014
- International Business Machines Corporation
- Raghu G. Gopalakrishnasetty
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
DYNAMICALLY POWER NOISE ADAPTIVE AUTOMATIC TEST PATTERN GENERATION
- Publication number 20200225283
- Publication date Jul 16, 2020
- International Business Machines Corporation
- Steven M. DOUSKEY
- G01 - MEASURING TESTING
Information Patent Application
OPERATING PULSED LATCHES ON A VARIABLE POWER SUPPLY
- Publication number 20190286221
- Publication date Sep 19, 2019
- International Business Machines Corporation
- STEVEN M. DOUSKEY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELF-MODERATING BUS ARBITRATION ARCHITECTURE
- Publication number 20190278728
- Publication date Sep 12, 2019
- International Business Machines Corporation
- Raghu G. GopalaKrishnaSetty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUIT STRUCTURES TO RESOLVE RANDOM TESTABILITY
- Publication number 20190056450
- Publication date Feb 21, 2019
- International Business Machines Corporation
- Raghu G. GopalaKrishnaSetty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUIT STRUCTURES TO RESOLVE RANDOM TESTABILITY
- Publication number 20190056449
- Publication date Feb 21, 2019
- International Business Machines Corporation
- Raghu G. GopalaKrishnaSetty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOGIC BUILT IN SELF TEST CIRCUITRY FOR USE IN AN INTEGRATED CIRCUIT...
- Publication number 20180306858
- Publication date Oct 25, 2018
- International Business Machines Corporation
- Satya R.S. Bhamidipati
- G01 - MEASURING TESTING
Information Patent Application
OPERATING PULSED LATCHES ON A VARIABLE POWER SUPPLY
- Publication number 20180196497
- Publication date Jul 12, 2018
- International Business Machines Corporation
- STEVEN M. DOUSKEY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADJUSTING SCAN CONNECTIONS BASED ON SCAN CONTROL LOCATIONS
- Publication number 20180096091
- Publication date Apr 5, 2018
- International Business Machines Corporation
- Raghu G. GopalaKrishnaSetty
- G01 - MEASURING TESTING
Information Patent Application
ADJUSTING LATENCY IN A SCAN CELL
- Publication number 20180052198
- Publication date Feb 22, 2018
- International Business Machines Corporation
- Steven M. DOUSKEY
- G01 - MEASURING TESTING
Information Patent Application
ADJUSTING LATENCY IN A SCAN CELL
- Publication number 20180052199
- Publication date Feb 22, 2018
- International Business Machines Corporation
- Steven M. DOUSKEY
- G01 - MEASURING TESTING
Information Patent Application
SELF-MODERATING BUS ARBITRATION ARCHITECTURE
- Publication number 20170270066
- Publication date Sep 21, 2017
- International Business Machines Corporation
- Raghu G. GopalaKrishnaSetty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOGIC BUILT IN SELF TEST CIRCUITRY FOR USE IN AN INTEGRATED CIRCUIT...
- Publication number 20170192054
- Publication date Jul 6, 2017
- International Business Machines Corporation
- Satya R.S. Bhamidipati
- G01 - MEASURING TESTING
Information Patent Application
LOGIC BUILT IN SELF TEST CIRCUITRY FOR USE IN AN INTEGRATED CIRCUIT...
- Publication number 20170192055
- Publication date Jul 6, 2017
- International Business Machines Corporation
- Satya R.S. Bhamidipati
- G01 - MEASURING TESTING
Information Patent Application
LOGIC BUILT IN SELF TEST CIRCUITRY FOR USE IN AN INTEGRATED CIRCUIT...
- Publication number 20170192057
- Publication date Jul 6, 2017
- International Business Machines Corporation
- Satya R.S. Bhamidipati
- G01 - MEASURING TESTING
Information Patent Application
ADJUSTING SCAN CONNECTIONS BASED ON SCAN CONTROL LOCATIONS
- Publication number 20170177777
- Publication date Jun 22, 2017
- International Business Machines Corporation
- Raghu G. GopalaKrishnaSetty
- G01 - MEASURING TESTING
Information Patent Application
CONTROL TEST POINT FOR TIMING STABILITY DURING SCAN CAPTURE
- Publication number 20150346281
- Publication date Dec 3, 2015
- International Business Machines Corporation
- Purushotam Bheemanna
- G01 - MEASURING TESTING
Information Patent Application
AUTOMATIC TEST PATTERN GENERATION (ATPG) CONSIDERING CROSSTALK EFFECTS
- Publication number 20150199466
- Publication date Jul 16, 2015
- International Business Machines Corporation
- Kanad Basu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTROL TEST POINT FOR TIMING STABILITY DURING SCAN CAPTURE
- Publication number 20150074477
- Publication date Mar 12, 2015
- International Business Machines Corporation
- Purushotam Bheemanna
- G01 - MEASURING TESTING
Information Patent Application
A Q-GATING CELL ARCHITECTURE TO SATIATE THE LAUNCH-OFF-SHIFT (LOS)...
- Publication number 20150067423
- Publication date Mar 5, 2015
- International Business Machines Corporation
- Raghu G. GopalaKrishnaSetty
- G01 - MEASURING TESTING

Raghu G. GopalaKrishnaSetty

Person

Patents Grantslast 30 patents

Operating pulsed latches on a variable power supply

Dynamically power noise adaptive automatic test pattern generation

Logic built in self test circuitry for use in an integrated circuit...

Logic built in self test circuitry for use in an integrated circuit...

Logic built in self test circuitry for use in an integrated circuit...

Circuit structures to resolve random testability

Circuit structures to resolve random testability

Self-moderating bus arbitration architecture

Operating pulsed latches on a variable power supply

Self-moderating bus arbitration architecture

Adjusting scan connections based on scan control locations

Logic built in self test circuitry for use in an integrated circuit...

Adjusting latency in a scan cell

Adjusting latency in a scan cell

Adjusting scan connections based on scan control locations

Control test point for timing stability during scan capture

Automatic test pattern generation (ATPG) considering crosstalk effects

Control test point for timing stability during scan capture

Q-gating cell architecture to satiate the launch-off-shift (LOS) te...

Algorithm to identify best Q-gating candidates and a Q-gating cell...

Delay defect testing of power drop effects in integrated circuits

Patents Applicationslast 30 patents

DYNAMICALLY POWER NOISE ADAPTIVE AUTOMATIC TEST PATTERN GENERATION

OPERATING PULSED LATCHES ON A VARIABLE POWER SUPPLY

SELF-MODERATING BUS ARBITRATION ARCHITECTURE

CIRCUIT STRUCTURES TO RESOLVE RANDOM TESTABILITY

CIRCUIT STRUCTURES TO RESOLVE RANDOM TESTABILITY

LOGIC BUILT IN SELF TEST CIRCUITRY FOR USE IN AN INTEGRATED CIRCUIT...

OPERATING PULSED LATCHES ON A VARIABLE POWER SUPPLY

ADJUSTING SCAN CONNECTIONS BASED ON SCAN CONTROL LOCATIONS

ADJUSTING LATENCY IN A SCAN CELL

ADJUSTING LATENCY IN A SCAN CELL

SELF-MODERATING BUS ARBITRATION ARCHITECTURE

LOGIC BUILT IN SELF TEST CIRCUITRY FOR USE IN AN INTEGRATED CIRCUIT...

LOGIC BUILT IN SELF TEST CIRCUITRY FOR USE IN AN INTEGRATED CIRCUIT...

LOGIC BUILT IN SELF TEST CIRCUITRY FOR USE IN AN INTEGRATED CIRCUIT...

ADJUSTING SCAN CONNECTIONS BASED ON SCAN CONTROL LOCATIONS

CONTROL TEST POINT FOR TIMING STABILITY DURING SCAN CAPTURE

AUTOMATIC TEST PATTERN GENERATION (ATPG) CONSIDERING CROSSTALK EFFECTS

CONTROL TEST POINT FOR TIMING STABILITY DURING SCAN CAPTURE

A Q-GATING CELL ARCHITECTURE TO SATIATE THE LAUNCH-OFF-SHIFT (LOS)...