RAGHU SANKURATRI

Person

SAN DIEGO, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for a shared cache with dynamic partitioning
- Patent number 10,089,238
- Issue date Oct 2, 2018
- QUALCOMM Incorporated
- Subbarao Palacharla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for a shared cache with adaptive partitioning
- Patent number 9,734,070
- Issue date Aug 15, 2017
- QUALCOMM Incorporated
- Alain Artieri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for flexible cache partitioning by sets and wa...
- Patent number 9,612,970
- Issue date Apr 4, 2017
- QUALCOMM Incorporated
- Subbarao Palacharla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low latency synchronization scheme for mesochronous DDR system
- Patent number 9,437,278
- Issue date Sep 6, 2016
- QUALCOMM Incorporated
- Edwin Jose
- G11 - INFORMATION STORAGE
Information Patent Grant
Low latency synchronization scheme for mesochronous DDR system
- Patent number 9,123,408
- Issue date Sep 1, 2015
- QUALCOMM Incorporated
- Edwin Jose
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual channel memory architecture having reduced interface pin requi...
- Patent number 8,325,525
- Issue date Dec 4, 2012
- QUALCOMM Incorporated
- Jian Mao
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Hybrid single and dual channel DDR interface scheme by interleaving...
- Patent number 8,098,539
- Issue date Jan 17, 2012
- QUALCOMM Incorporated
- Raghu Sankuratri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual channel memory architecture having a reduced interface pin req...
- Patent number 7,804,735
- Issue date Sep 28, 2010
- QUALCOMM Incorporated
- Jian Mao
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Mobile communication device having dual micro processor architectur...
- Patent number 6,754,509
- Issue date Jun 22, 2004
- Qualcomm, Incorporated
- Safi Khan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for activating a high frequency clock followin...
- Patent number 6,735,454
- Issue date May 11, 2004
- Qualcomm, Incorporated
- Nicholas K. Yu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
SYSTEM AND METHOD FOR A SHARED CACHE WITH ADAPTIVE PARTITIONING
- Publication number 20170116118
- Publication date Apr 27, 2017
- QUALCOMM Incorporated
- ALAIN ARTIERI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC RANDOM ACCESS MEMORY TIMING ADJUSTMENTS
- Publication number 20160093345
- Publication date Mar 31, 2016
- QUALCOMM Incorporated
- Dexter Tamio Chun
- G11 - INFORMATION STORAGE
Information Patent Application
Method And Apparatus For A Shared Cache With Dynamic Partitioning
- Publication number 20160019158
- Publication date Jan 21, 2016
- QUALCOMM Incorporated
- Subbarao Palacharla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus For Flexible Cache Partitioning By Sets And Wa...
- Publication number 20160019157
- Publication date Jan 21, 2016
- QUALCOMM Incorporated
- Subbarao Palacharla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW LATENCY SYNCHRONIZATION SCHEME FOR MESOCHRONOUS DDR SYSTEM
- Publication number 20150340078
- Publication date Nov 26, 2015
- QUALCOMM Incorporated
- Edwin Jose
- G11 - INFORMATION STORAGE
Information Patent Application
LOW LATENCY SYNCHRONIZATION SCHEME FOR MESOCHRONOUS DDR SYSTEM
- Publication number 20140347941
- Publication date Nov 27, 2014
- QUALCOMM Incorporated
- Edwin Jose
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Hybrid Single and Dual Channel DDR Interface Scheme by Interleaving...
- Publication number 20110055617
- Publication date Mar 3, 2011
- QUALCOMM Incorporated
- Raghu Sankuratri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dual Channel Memory Architecture Having Reduced Interface Pin Requi...
- Publication number 20100318730
- Publication date Dec 16, 2010
- QUALCOMM Incorporated
- Jian Mao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dual Channel Memory Architecture Having a Reduced Interface Pin Req...
- Publication number 20090219779
- Publication date Sep 3, 2009
- QUALCOMM Incorporated
- Jian Mao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Calibrating an integrated circuit to an electronic device
- Publication number 20050114725
- Publication date May 26, 2005
- Qualcomm, Inc.
- Jagrut V. Patel
- G01 - MEASURING TESTING

RAGHU SANKURATRI

Person

Patents Grantslast 30 patents

Method and apparatus for a shared cache with dynamic partitioning

System and method for a shared cache with adaptive partitioning

Method and apparatus for flexible cache partitioning by sets and wa...

Low latency synchronization scheme for mesochronous DDR system

Low latency synchronization scheme for mesochronous DDR system

Dual channel memory architecture having reduced interface pin requi...

Hybrid single and dual channel DDR interface scheme by interleaving...

Dual channel memory architecture having a reduced interface pin req...

Mobile communication device having dual micro processor architectur...

Method and apparatus for activating a high frequency clock followin...

Patents Applicationslast 30 patents

SYSTEM AND METHOD FOR A SHARED CACHE WITH ADAPTIVE PARTITIONING

DYNAMIC RANDOM ACCESS MEMORY TIMING ADJUSTMENTS

Method And Apparatus For A Shared Cache With Dynamic Partitioning

Method and Apparatus For Flexible Cache Partitioning By Sets And Wa...

LOW LATENCY SYNCHRONIZATION SCHEME FOR MESOCHRONOUS DDR SYSTEM

LOW LATENCY SYNCHRONIZATION SCHEME FOR MESOCHRONOUS DDR SYSTEM

Hybrid Single and Dual Channel DDR Interface Scheme by Interleaving...

Dual Channel Memory Architecture Having Reduced Interface Pin Requi...

Dual Channel Memory Architecture Having a Reduced Interface Pin Req...

Calibrating an integrated circuit to an electronic device