Raghunandan CHAWARE

Person

Fremont, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Die singulation and stacked device structures
- Patent number 11,075,117
- Issue date Jul 27, 2021
- Xilinx, Inc.
- Ganesh Hariharan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked silicon package assembly having enhanced stiffener
- Patent number 10,840,192
- Issue date Nov 17, 2020
- Xilinx, Inc.
- Nael Zohni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnect frames for SIP modules
- Patent number 10,638,608
- Issue date Apr 28, 2020
- Apple Inc.
- Lan H. Hoang
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Vertical module and perpendicular pin array interconnect for stacke...
- Patent number 10,602,612
- Issue date Mar 24, 2020
- Apple Inc.
- Lan H. Hoang
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Temporary connection traces for wafer sort testing
- Patent number 10,204,841
- Issue date Feb 12, 2019
- Xilinx, Inc.
- Matthew H. Klein
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-die wafer-level test and assembly without comprehensive indiv...
- Patent number 10,032,682
- Issue date Jul 24, 2018
- Xilinx, Inc.
- Matthew H. Klein
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for testing interposer dies prior to assembly
- Patent number 9,989,572
- Issue date Jun 5, 2018
- Xilinx, Inc.
- Raghunandan Chaware
- G01 - MEASURING TESTING
Information Patent Grant
Heterogeneous integration of integrated circuit device and companio...
- Patent number 9,865,567
- Issue date Jan 9, 2018
- Xilinx, Inc.
- Raghunandan Chaware
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interposer-less stack die interconnect
- Patent number 9,761,533
- Issue date Sep 12, 2017
- Xilinx, Inc.
- Raghunandan Chaware
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked silicon package assembly having enhanced lid adhesion
- Patent number 9,418,909
- Issue date Aug 16, 2016
- Xilinx, Inc.
- Raghunandan Chaware
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for providing charge protection to one or more dies during f...
- Patent number 9,385,106
- Issue date Jul 5, 2016
- Xilinx, Inc.
- Raghunandan Chaware
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package testing
- Patent number 9,341,668
- Issue date May 17, 2016
- XILNIX, INC.
- Ganesh Hariharan
- G01 - MEASURING TESTING
Information Patent Grant
Method for removing bumps from incomplete and defective interposer...
- Patent number 8,900,987
- Issue date Dec 2, 2014
- Xilinx, Inc.
- Inderjit Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure and method for interconnection of integrate...
- Patent number 8,841,752
- Issue date Sep 23, 2014
- Xilinx, Inc.
- Raghunandan Chaware
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System and method for laminating photovoltaic structures
- Patent number 8,766,086
- Issue date Jul 1, 2014
- Solaria Corporation
- Abhay Maheshwari
- B32 - LAYERED PRODUCTS
Information Patent Grant
Stacked die assembly
- Patent number 8,704,384
- Issue date Apr 22, 2014
- Xilinx, Inc.
- Ephrem C. Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure and method for interconnection of integrate...
- Patent number 8,519,528
- Issue date Aug 27, 2013
- Xilinx, Inc.
- Kumar Nagarajan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus and methodology for testing stacked die
- Patent number 8,415,783
- Issue date Apr 9, 2013
- Xilinx, Inc.
- Arifur Rahman
- G01 - MEASURING TESTING
Information Patent Grant
System and method for determining placement of photovoltaic strips...
- Patent number 8,361,259
- Issue date Jan 29, 2013
- Solaria Corporation
- Shirish Shah
- B32 - LAYERED PRODUCTS
Information Patent Grant
Molded integrated circuit package and method of forming a molded in...
- Patent number 7,906,857
- Issue date Mar 15, 2011
- Xilinx, Inc.
- Lan H. Hoang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low cost bumping and bonding method for stacked die
- Patent number 7,863,092
- Issue date Jan 4, 2011
- Xilinx, Inc.
- Raghunandan Chaware
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
BOARD-TO-BOARD (B2B) CONNECTOR FOR IMPROVED PERFORMANCE AND STRENGT...
- Publication number 20220344861
- Publication date Oct 27, 2022
- Verre.io, Inc.
- Raghunandan Chaware
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIE SINGULATION AND STACKED DEVICE STRUCTURES
- Publication number 20190267287
- Publication date Aug 29, 2019
- Xilinx, Inc.
- Ganesh Hariharan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERCONNECT FRAMES FOR SIP MODULES
- Publication number 20190082538
- Publication date Mar 14, 2019
- Apple Inc.
- Lan H. Hoang
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
INTERPOSER-LESS STACK DIE INTERCONNECT
- Publication number 20170110407
- Publication date Apr 20, 2017
- Xilinx, Inc.
- Raghunandan Chaware
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEM AND METHOD FOR LAMINATING PHOTOVOLTAIC STRUCTURES
- Publication number 20140312530
- Publication date Oct 23, 2014
- Abhay MAHESHWARI
- B32 - LAYERED PRODUCTS
Information Patent Application
STACKED DIE ASSEMBLY
- Publication number 20130214432
- Publication date Aug 22, 2013
- Xilinx, Inc.
- Ephrem C. Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEM AND METHOD FOR DETERMINING PLACEMENT OF PHOTOVOLTAIC STRIPS...
- Publication number 20130206208
- Publication date Aug 15, 2013
- Solaria Corporation
- Shirish Shah
- B32 - LAYERED PRODUCTS
Information Patent Application
PHOTOVOLTAIC STRIP SOLAR MODULES AND METHODS
- Publication number 20120211052
- Publication date Aug 23, 2012
- Solaria Corporation
- Ajay MARATHE
- G02 - OPTICS
Information Patent Application
SYSTEM AND METHOD FOR FORMING PHOTOVOLTAIC MODULES
- Publication number 20120167948
- Publication date Jul 5, 2012
- Solaria Corporation
- Ajay Marathe
- G02 - OPTICS
Information Patent Application
SYSTEM AND METHOD FOR DETERMINING PLACEMENT OF PHOTOVOLTAIC STRIPS...
- Publication number 20120067397
- Publication date Mar 22, 2012
- Solaria Corporation
- Shirish Shah
- B32 - LAYERED PRODUCTS
Information Patent Application
SYSTEM AND METHOD FOR LAMINATING PHOTOVOLTAIC STRUCTURES
- Publication number 20120067398
- Publication date Mar 22, 2012
- Solaria Corporation
- Abhay MAHESHWARI
- B32 - LAYERED PRODUCTS

Raghunandan CHAWARE

Person

Patents Grantslast 30 patents

Die singulation and stacked device structures

Stacked silicon package assembly having enhanced stiffener

Interconnect frames for SIP modules

Vertical module and perpendicular pin array interconnect for stacke...

Temporary connection traces for wafer sort testing

Multi-die wafer-level test and assembly without comprehensive indiv...

Method and apparatus for testing interposer dies prior to assembly

Heterogeneous integration of integrated circuit device and companio...

Interposer-less stack die interconnect

Stacked silicon package assembly having enhanced lid adhesion

Method for providing charge protection to one or more dies during f...

Integrated circuit package testing

Method for removing bumps from incomplete and defective interposer...

Semiconductor structure and method for interconnection of integrate...

System and method for laminating photovoltaic structures

Stacked die assembly

Semiconductor structure and method for interconnection of integrate...

Apparatus and methodology for testing stacked die

System and method for determining placement of photovoltaic strips...

Molded integrated circuit package and method of forming a molded in...

Low cost bumping and bonding method for stacked die

Patents Applicationslast 30 patents

BOARD-TO-BOARD (B2B) CONNECTOR FOR IMPROVED PERFORMANCE AND STRENGT...

DIE SINGULATION AND STACKED DEVICE STRUCTURES

INTERCONNECT FRAMES FOR SIP MODULES

INTERPOSER-LESS STACK DIE INTERCONNECT

SYSTEM AND METHOD FOR LAMINATING PHOTOVOLTAIC STRUCTURES

STACKED DIE ASSEMBLY

SYSTEM AND METHOD FOR DETERMINING PLACEMENT OF PHOTOVOLTAIC STRIPS...

PHOTOVOLTAIC STRIP SOLAR MODULES AND METHODS

SYSTEM AND METHOD FOR FORMING PHOTOVOLTAIC MODULES

SYSTEM AND METHOD FOR DETERMINING PLACEMENT OF PHOTOVOLTAIC STRIPS...

SYSTEM AND METHOD FOR LAMINATING PHOTOVOLTAIC STRUCTURES