Raguram Damodaran

Person

San Diego, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Providing load address predictions using address prediction tables...
- Patent number 11,709,679
- Issue date Jul 25, 2023
- QUALCOMM Incorporated
- Rami Mohammad Al Sheikh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Lookahead priority collection to support priority elevation
- Patent number 10,713,180
- Issue date Jul 14, 2020
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for dynamic clock and voltage scaling in a com...
- Patent number 10,551,896
- Issue date Feb 4, 2020
- QUALCOMM Incorporated
- Shivam Priyadarshi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic pipeline throttling using confidence-based weighting of in-...
- Patent number 10,474,462
- Issue date Nov 12, 2019
- QUALCOMM Incorporated
- Shivam Priyadarshi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Providing references to previously decoded instructions of recently...
- Patent number 10,223,118
- Issue date Mar 5, 2019
- QUALCOMM Incorporated
- Vignyan Reddy Kothinti Naresh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for dynamic power reduction in a unified sched...
- Patent number 10,203,745
- Issue date Feb 12, 2019
- QUALCOMM Incorporated
- Milind Ram Kulkarni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Storing narrow produced values for instruction operands directly in...
- Patent number 10,108,417
- Issue date Oct 23, 2018
- QUALCOMM Incorporated
- Anil Krishna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple instruction issuance with parallel inter-group and intra-g...
- Patent number 10,089,114
- Issue date Oct 2, 2018
- QUALCOMM Incorporated
- Milind Ram Kulkarni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory attribute sharing between differing cache levels of multilev...
- Patent number 9,965,395
- Issue date May 8, 2018
- Texas Instruments Incorporated
- Raguram Damodaran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for dynamic clock and voltage scaling in a com...
- Patent number 9,851,774
- Issue date Dec 26, 2017
- QUALCOMM Incorporated
- Shivam Priyadarshi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selective storing of previously decoded instructions of frequently-...
- Patent number 9,830,152
- Issue date Nov 28, 2017
- QUALCOMM Incorporated
- Vignyan Reddy Kothinti Naresh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Speculative history forwarding in overriding branch predictors, and...
- Patent number 9,582,285
- Issue date Feb 28, 2017
- QUALCOMM Incorporated
- Rami Mohammad Al Sheikh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable address-based write-through cache control
- Patent number 9,575,901
- Issue date Feb 21, 2017
- Texas Instruments Incorporated
- Raguram Damodaran
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Distributed power control for controlling power consumption based o...
- Patent number RE46193
- Issue date Nov 1, 2016
- Texas Instruments Incorporated
- Timothy David Anderson
Information Patent Grant
Zero cycle clock invalidate operation
- Patent number 9,390,011
- Issue date Jul 12, 2016
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Performance and power improvement on DMA writes to level two combin...
- Patent number 9,298,643
- Issue date Mar 29, 2016
- Texas Instruments Incorporated
- Jonathan (Son) Hung Tran
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Level one data cache line lock and enhanced snoop protocol during c...
- Patent number 9,268,708
- Issue date Feb 23, 2016
- Texas Instruments Incorporated
- Raguram Damodaran
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Zero cycle clock invalidate operation
- Patent number 9,244,837
- Issue date Jan 26, 2016
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transaction info bypass for nodes coupled to an interconnect fabric
- Patent number 9,195,610
- Issue date Nov 24, 2015
- Texas Instruments Incorporated
- Dheera Balasubramanian
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Programmable address-based write-through cache control
- Patent number 9,189,331
- Issue date Nov 17, 2015
- Texas Instruments Incorporated
- Raguram Damodaran
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Memory attribute sharing between differing cache levels of multilev...
- Patent number 9,183,084
- Issue date Nov 10, 2015
- Texas Instruments Incorporated
- Raguram Damodaran
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Managing bandwidth allocation in a processing node using distribute...
- Patent number 9,075,743
- Issue date Jul 7, 2015
- Texas Instruments Incorporated
- Raguram Damodaran
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Performance and power improvement on DMA writes to level two combin...
- Patent number 9,075,744
- Issue date Jul 7, 2015
- Texas Instruments Incorporated
- Jonathan (Son) Hung Tran
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
pBIST architecture with multiple asynchronous sub chips operating i...
- Patent number 9,021,320
- Issue date Apr 28, 2015
- Texas Instruments Incorporated
- Raguram Damodaran
- G11 - INFORMATION STORAGE
Information Patent Grant
pBIST engine with distributed data logging
- Patent number 9,009,550
- Issue date Apr 14, 2015
- Texas Instruments Incorporated
- Raguram Damodaran
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-blocking, pipelined write allocates with allocate data merging...
- Patent number 9,009,408
- Issue date Apr 14, 2015
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Level one data cache line lock and enhanced snoop protocol during c...
- Patent number 9,003,122
- Issue date Apr 7, 2015
- Texas Instruments Incorporated
- Raguram Damodaran
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
pBIST engine with reduced SRAM testing bus width
- Patent number 8,977,915
- Issue date Mar 10, 2015
- Texas Instruments Incorporated
- Raguram Damodaran
- G11 - INFORMATION STORAGE
Information Patent Grant
Parallel processing of multiple block coherence operations
- Patent number 8,977,821
- Issue date Mar 10, 2015
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Asynchronous clock dividers to reduce on-chip variations of clock t...
- Patent number 8,970,267
- Issue date Mar 3, 2015
- Texas Instruments Incorporated
- Raguram Damodaran
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
LOOKAHEAD PRIORITY COLLECTION TO SUPPORT PRIORITY ELEVATION
- Publication number 20230244611
- Publication date Aug 3, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOOKAHEAD PRIORITY COLLECTION TO SUPPORT PRIORITY ELEVATION
- Publication number 20200401532
- Publication date Dec 24, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Lookahead Priority Collection to Support Priority Elevation
- Publication number 20190004967
- Publication date Jan 3, 2019
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok Chachad
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Memory Attribute Sharing Between Differing Cache Levels of Multilev...
- Publication number 20180129608
- Publication date May 10, 2018
- TEXAS INSTRUMENTS INCORPORATED
- Raguram Damodaran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REPLAYING SPECULATIVELY DISPATCHED LOAD-DEPENDENT INSTRUCTIONS IN R...
- Publication number 20180081691
- Publication date Mar 22, 2018
- QUALCOMM Incorporated
- Milind Ram Kulkarni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR DYNAMIC CLOCK AND VOLTAGE SCALING IN A COM...
- Publication number 20180074568
- Publication date Mar 15, 2018
- QUALCOMM Incorporated
- Shivam PRIYADARSHI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROVIDING LOAD ADDRESS PREDICTIONS USING ADDRESS PREDICTION TABLES...
- Publication number 20170286119
- Publication date Oct 5, 2017
- QUALCOMM Incorporated
- Rami Mohammad Al Sheikh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD TO MAXIMIZE EXECUTION LANE UTILIZATION THROUGH...
- Publication number 20170286120
- Publication date Oct 5, 2017
- QUALCOMM Incorporated
- Milind Ram KULKARNI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR DYNAMIC POWER REDUCTION IN A UNIFIED SCHED...
- Publication number 20170285727
- Publication date Oct 5, 2017
- QUALCOMM Incorporated
- Milind Ram KULKARNI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROVIDING REFERENCES TO PREVIOUSLY DECODED INSTRUCTIONS OF RECENTLY...
- Publication number 20170277536
- Publication date Sep 28, 2017
- QUALCOMM Incorporated
- Vignyan Reddy Kothinti Naresh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC PIPELINE THROTTLING USING CONFIDENCE-BASED WEIGHTING OF IN-...
- Publication number 20170249149
- Publication date Aug 31, 2017
- QUALCOMM Incorporated
- Shivam PRIYADARSHI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR DYNAMIC CLOCK AND VOLTAGE SCALING IN A COM...
- Publication number 20170192484
- Publication date Jul 6, 2017
- QUALCOMM Incorporated
- Shivam Priyadarshi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELECTIVE STORING OF PREVIOUSLY DECODED INSTRUCTIONS OF FREQUENTLY-...
- Publication number 20170177366
- Publication date Jun 22, 2017
- QUALCOMM Incorporated
- Vignyan Reddy Kothinti Naresh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Attribute Sharing Between Differing Cache Levels of Multilev...
- Publication number 20170097894
- Publication date Apr 6, 2017
- TEXAS INSTRUMENTS INCORPORATED
- Raguram Damodaran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR CACHE LINE DEDUPLICATION VIA DATA MATCHING
- Publication number 20170091117
- Publication date Mar 30, 2017
- QUALCOMM Incorporated
- Harold Wade CAIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RECONFIGURING EXECUTION PIPELINES OF OUT-OF-ORDER (OOO) COMPUTER PR...
- Publication number 20170090930
- Publication date Mar 30, 2017
- QUALCOMM Incoporated
- Shivam Priyadarshi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR EFFECTIVE CLOCK SCALING AT EXPOSED CACHE S...
- Publication number 20170090508
- Publication date Mar 30, 2017
- QUALCOMM Incorporated
- Shivam PRIYADARSHI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIERARCHICAL REGISTER FILE SYSTEM
- Publication number 20170060593
- Publication date Mar 2, 2017
- QUALCOMM Incorporated
- Anil KRISHNA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STORING NARROW PRODUCED VALUES FOR INSTRUCTION OPERANDS DIRECTLY IN...
- Publication number 20170046154
- Publication date Feb 16, 2017
- QUALCOMM Incorporated
- Anil Krishna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER EFFICIENT FETCH ADAPTATION
- Publication number 20170046159
- Publication date Feb 16, 2017
- QUALCOMM Incorporated
- Shivam PRIYADARSHI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Programmable Address-Based Write-Through Cache Control
- Publication number 20160034396
- Publication date Feb 4, 2016
- TEXAS INSTRUMENTS INCORPORATED
- Raguram Damodaran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ZERO CYCLE CLOCK INVALIDATE OPERATION
- Publication number 20160026569
- Publication date Jan 28, 2016
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPECULATIVE HISTORY FORWARDING IN OVERRIDING BRANCH PREDICTORS, AND...
- Publication number 20150268958
- Publication date Sep 24, 2015
- QUALCOMM Incorporated
- Rami Mohammad Al Sheikh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERFORMANCE AND POWER IMPROVEMENT ON DMA WRITES TO LEVEL TWO COMBIN...
- Publication number 20150269090
- Publication date Sep 24, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Jonathan (Son) Hung Tran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Level One Data Cache Line Lock and Enhanced Snoop Protocol During C...
- Publication number 20150178221
- Publication date Jun 25, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Raguram Damodaran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC MANAGEMENT OF WRITE-MISS BUFFER TO REDUCE WRITE-MISS TRAFFIC
- Publication number 20150006820
- Publication date Jan 1, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
pBIST ENGINE WITH DISTRIBUTED DATA LOGGING
- Publication number 20140164844
- Publication date Jun 12, 2014
- TEXAS INSTRUMENTS INCORPORATED
- Raguram Damodaran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
pBIST READ ONLY MEMORY IMAGE COMPRESSION
- Publication number 20140164855
- Publication date Jun 12, 2014
- TEXAS INSTRUMENTS INCORPORATED
- Raguram Damodaran
- G01 - MEASURING TESTING
Information Patent Application
pBIST ENGINE WITH REDUCED SRAM TESTING BUS WIDTH
- Publication number 20140164856
- Publication date Jun 12, 2014
- TEXAS INSTRUMENTS INCORPORATED
- Raguram Damodaran
- G11 - INFORMATION STORAGE
Information Patent Application
pBIST ARCHITECTURE WITH MULTIPLE ASYNCHRONOUS SUB CHIPS OPERATING I...
- Publication number 20140164854
- Publication date Jun 12, 2014
- TEXAS INSTRUMENTS INCORPORATED
- Raguram Damodaran
- G11 - INFORMATION STORAGE

Raguram Damodaran

Person

Patents Grantslast 30 patents

Providing load address predictions using address prediction tables...

Lookahead priority collection to support priority elevation

Method and apparatus for dynamic clock and voltage scaling in a com...

Dynamic pipeline throttling using confidence-based weighting of in-...

Providing references to previously decoded instructions of recently...

Apparatus and method for dynamic power reduction in a unified sched...

Storing narrow produced values for instruction operands directly in...

Multiple instruction issuance with parallel inter-group and intra-g...

Memory attribute sharing between differing cache levels of multilev...

Method and apparatus for dynamic clock and voltage scaling in a com...

Selective storing of previously decoded instructions of frequently-...

Speculative history forwarding in overriding branch predictors, and...

Programmable address-based write-through cache control

Distributed power control for controlling power consumption based o...

Zero cycle clock invalidate operation

Performance and power improvement on DMA writes to level two combin...

Level one data cache line lock and enhanced snoop protocol during c...

Zero cycle clock invalidate operation

Transaction info bypass for nodes coupled to an interconnect fabric

Programmable address-based write-through cache control

Memory attribute sharing between differing cache levels of multilev...

Managing bandwidth allocation in a processing node using distribute...

Performance and power improvement on DMA writes to level two combin...

pBIST architecture with multiple asynchronous sub chips operating i...

pBIST engine with distributed data logging

Non-blocking, pipelined write allocates with allocate data merging...

Level one data cache line lock and enhanced snoop protocol during c...

pBIST engine with reduced SRAM testing bus width

Parallel processing of multiple block coherence operations

Asynchronous clock dividers to reduce on-chip variations of clock t...

Patents Applicationslast 30 patents

LOOKAHEAD PRIORITY COLLECTION TO SUPPORT PRIORITY ELEVATION

LOOKAHEAD PRIORITY COLLECTION TO SUPPORT PRIORITY ELEVATION

Lookahead Priority Collection to Support Priority Elevation

Memory Attribute Sharing Between Differing Cache Levels of Multilev...

REPLAYING SPECULATIVELY DISPATCHED LOAD-DEPENDENT INSTRUCTIONS IN R...

METHOD AND APPARATUS FOR DYNAMIC CLOCK AND VOLTAGE SCALING IN A COM...

PROVIDING LOAD ADDRESS PREDICTIONS USING ADDRESS PREDICTION TABLES...

APPARATUS AND METHOD TO MAXIMIZE EXECUTION LANE UTILIZATION THROUGH...

APPARATUS AND METHOD FOR DYNAMIC POWER REDUCTION IN A UNIFIED SCHED...

PROVIDING REFERENCES TO PREVIOUSLY DECODED INSTRUCTIONS OF RECENTLY...

DYNAMIC PIPELINE THROTTLING USING CONFIDENCE-BASED WEIGHTING OF IN-...

METHOD AND APPARATUS FOR DYNAMIC CLOCK AND VOLTAGE SCALING IN A COM...

SELECTIVE STORING OF PREVIOUSLY DECODED INSTRUCTIONS OF FREQUENTLY-...

Memory Attribute Sharing Between Differing Cache Levels of Multilev...

METHOD AND APPARATUS FOR CACHE LINE DEDUPLICATION VIA DATA MATCHING

RECONFIGURING EXECUTION PIPELINES OF OUT-OF-ORDER (OOO) COMPUTER PR...

METHOD AND APPARATUS FOR EFFECTIVE CLOCK SCALING AT EXPOSED CACHE S...

HIERARCHICAL REGISTER FILE SYSTEM

STORING NARROW PRODUCED VALUES FOR INSTRUCTION OPERANDS DIRECTLY IN...

POWER EFFICIENT FETCH ADAPTATION

Programmable Address-Based Write-Through Cache Control

ZERO CYCLE CLOCK INVALIDATE OPERATION

SPECULATIVE HISTORY FORWARDING IN OVERRIDING BRANCH PREDICTORS, AND...

PERFORMANCE AND POWER IMPROVEMENT ON DMA WRITES TO LEVEL TWO COMBIN...

Level One Data Cache Line Lock and Enhanced Snoop Protocol During C...

DYNAMIC MANAGEMENT OF WRITE-MISS BUFFER TO REDUCE WRITE-MISS TRAFFIC

pBIST ENGINE WITH DISTRIBUTED DATA LOGGING

pBIST READ ONLY MEMORY IMAGE COMPRESSION

pBIST ENGINE WITH REDUCED SRAM TESTING BUS WIDTH

pBIST ARCHITECTURE WITH MULTIPLE ASYNCHRONOUS SUB CHIPS OPERATING I...