Rahul Gulati

Person

Bangalore, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit chip with cores asymmetrically oriented with res...
- Patent number 11,698,841
- Issue date Jul 11, 2023
- Texas Instruments Incorporated
- Jasbir Singh Nayyar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Package on package memory interface and configuration with error co...
- Patent number 11,662,211
- Issue date May 30, 2023
- Texas Instruments Incorporated
- Rahul Gulati
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit chip with cores asymmetrically oriented with res...
- Patent number 11,269,742
- Issue date Mar 8, 2022
- Texas Instruments Incorporated
- Jasbir Singh Nayyar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Package on package memory interface and configuration with error co...
- Patent number 10,767,998
- Issue date Sep 8, 2020
- Texas Instruments Incorporated
- Rahul Gulati
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit chip with cores asymmetrically oriented with res...
- Patent number 10,649,865
- Issue date May 12, 2020
- Texas Instruments Incorporated
- Jasbir Singh Nayyar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Package on package memory interface and configuration with error co...
- Patent number 10,089,172
- Issue date Oct 2, 2018
- Texas Instruments Incorporated
- Rahul Gulati
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for implementing error correcting code in a memory
- Patent number 10,061,644
- Issue date Aug 28, 2018
- QUALCOMM Incorporated
- Nhon Quach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit chip with cores asymmetrically oriented with res...
- Patent number 10,002,056
- Issue date Jun 19, 2018
- Texas Instruments Incorporated
- Jasbir Singh Nayyar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for implementing error correcting code regions...
- Patent number 9,983,930
- Issue date May 29, 2018
- QUALCOMM Incorporated
- Nhon Quach
- G11 - INFORMATION STORAGE
Information Patent Grant
Testing of display subsystems
- Patent number 9,955,150
- Issue date Apr 24, 2018
- QUALCOMM Incorporated
- Rahul Gulati
- B60 - VEHICLES IN GENERAL
Information Patent Grant
Ultra-fast autonomous clock monitoring circuit for safe and secure...
- Patent number 9,897,651
- Issue date Feb 20, 2018
- QUALCOMM Incorporated
- Virendra Bansal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
On-chip field testing methods and apparatus
- Patent number 9,836,373
- Issue date Dec 5, 2017
- Texas Instruments Incorporated
- Srinivas Kumar Vooka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Ensuring imaging subsystem integrity in camera based safety systems
- Patent number 9,628,787
- Issue date Apr 18, 2017
- Texas Instruments Incorporated
- Rahul Gulati
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
System and method for managing cache
- Patent number 9,430,393
- Issue date Aug 30, 2016
- Texas Instruments Incorporated
- Prashant Dinkar Karandikar
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Integrated Circuit Chip with Cores Asymmetrically Oriented With Res...
- Publication number 20230297480
- Publication date Sep 21, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Jasbir Singh Nayyar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Package On Package Memory Interface and Configuration With Error Co...
- Publication number 20230258454
- Publication date Aug 17, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Rahul Gulati
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrated Circuit Chip with Cores Asymmetrically Oriented With Res...
- Publication number 20220147424
- Publication date May 12, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Jasbir Singh Nayyar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Package On Package Memory Interface and Configuration With Error Co...
- Publication number 20200363210
- Publication date Nov 19, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Rahul Gulati
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrated Circuit Chip with Cores Asymmetrically Oriented With Res...
- Publication number 20200233758
- Publication date Jul 23, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Jasbir Singh Nayyar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Package On Package Memory Interface and Configuration With Error Co...
- Publication number 20180364051
- Publication date Dec 20, 2018
- TEXAS INSTRUMENTS INCORPORATED
- Rahul Gulati
- G01 - MEASURING TESTING
Information Patent Application
Integrated Circuit Chip with Multiple Cores
- Publication number 20180285218
- Publication date Oct 4, 2018
- TEXAS INSTRUMENTS INCORPORATED
- Jasbir Singh Nayyar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR IMPLEMENTING ERROR CORRECTING CODE REGIONS...
- Publication number 20180032394
- Publication date Feb 1, 2018
- QUALCOMM Incorporated
- NHON QUACH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Ultra-Fast Autonomous Clock Monitoring Circuit for Safe and Secure...
- Publication number 20170255223
- Publication date Sep 7, 2017
- QUALCOMM Incorporated
- Virendra Bansal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHORT-RESISTANT OUTPUT PIN CIRCUITRY
- Publication number 20170222430
- Publication date Aug 3, 2017
- QUALCOMM Incorporated
- Virendra Bansal
- G01 - MEASURING TESTING
Information Patent Application
SYSTEMS AND METHODS FOR IMPLEMENTING ERROR CORRECTING CODE IN A MEMORY
- Publication number 20170123897
- Publication date May 4, 2017
- QUALCOMM Incorporated
- Nhon Quach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TESTING OF DISPLAY SUBSYSTEMS
- Publication number 20170094268
- Publication date Mar 30, 2017
- QUALCOMM Incorporated
- Rahul Gulati
- B60 - VEHICLES IN GENERAL
Information Patent Application
INTEGRATED CIRCUIT CHIP WITH MULTIPLE CORES
- Publication number 20170074930
- Publication date Mar 16, 2017
- TEXAS INSTRUMENTS INCORPORATED
- JASBIR SINGH NAYYAR
- G01 - MEASURING TESTING
Information Patent Application
ON-CHIP FIELD TESTING METHODS AND APPARATUS
- Publication number 20160146888
- Publication date May 26, 2016
- TEXAS INSTRUMENTS INCORPORATED
- Srinivas Kumar Vooka
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM AND METHOD FOR MANAGING CACHE
- Publication number 20150339234
- Publication date Nov 26, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Prashant Dinkar Karandikar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Ensuring Imaging Subsystem Integrity in Camera Based Safety Systems
- Publication number 20150304648
- Publication date Oct 22, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Rahul Gulati
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Package On Package Memory Interface and Configuration With Error Co...
- Publication number 20150227421
- Publication date Aug 13, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Rahul Gulati
- G06 - COMPUTING CALCULATING COUNTING

Rahul Gulati

Person

Patents Grantslast 30 patents

Integrated circuit chip with cores asymmetrically oriented with res...

Package on package memory interface and configuration with error co...

Integrated circuit chip with cores asymmetrically oriented with res...

Package on package memory interface and configuration with error co...

Integrated circuit chip with cores asymmetrically oriented with res...

Package on package memory interface and configuration with error co...

Systems and methods for implementing error correcting code in a memory

Integrated circuit chip with cores asymmetrically oriented with res...

Systems and methods for implementing error correcting code regions...

Testing of display subsystems

Ultra-fast autonomous clock monitoring circuit for safe and secure...

On-chip field testing methods and apparatus

Ensuring imaging subsystem integrity in camera based safety systems

System and method for managing cache

Patents Applicationslast 30 patents

Integrated Circuit Chip with Cores Asymmetrically Oriented With Res...

Package On Package Memory Interface and Configuration With Error Co...

Integrated Circuit Chip with Cores Asymmetrically Oriented With Res...

Package On Package Memory Interface and Configuration With Error Co...

Integrated Circuit Chip with Cores Asymmetrically Oriented With Res...

Package On Package Memory Interface and Configuration With Error Co...

Integrated Circuit Chip with Multiple Cores

SYSTEMS AND METHODS FOR IMPLEMENTING ERROR CORRECTING CODE REGIONS...

Ultra-Fast Autonomous Clock Monitoring Circuit for Safe and Secure...

SHORT-RESISTANT OUTPUT PIN CIRCUITRY

SYSTEMS AND METHODS FOR IMPLEMENTING ERROR CORRECTING CODE IN A MEMORY

TESTING OF DISPLAY SUBSYSTEMS

INTEGRATED CIRCUIT CHIP WITH MULTIPLE CORES

ON-CHIP FIELD TESTING METHODS AND APPARATUS

SYSTEM AND METHOD FOR MANAGING CACHE

Ensuring Imaging Subsystem Integrity in Camera Based Safety Systems

Package On Package Memory Interface and Configuration With Error Co...