Rahul Mathur

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Burst read with flexible burst length for on-chip memory
- Patent number 12,087,353
- Issue date Sep 10, 2024
- ARM Limited
- Edward Martin McCombs
- G11 - INFORMATION STORAGE
Information Patent Grant
Power-up header circuitry for multi-bank memory
- Patent number 12,068,025
- Issue date Aug 20, 2024
- ARM Limited
- Rahul Mathur
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-tier memory architecture
- Patent number 11,682,432
- Issue date Jun 20, 2023
- ARM Limited
- Supreet Jeloka
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-tier memory architecture
- Patent number 11,670,363
- Issue date Jun 6, 2023
- ARM Limited
- Rahul Mathur
- G11 - INFORMATION STORAGE
Information Patent Grant
TSV coupled integrated circuits and methods
- Patent number 11,569,219
- Issue date Jan 31, 2023
- ARM Limited
- Rahul Mathur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuitry apportioning of an integrated circuit
- Patent number 11,532,353
- Issue date Dec 20, 2022
- ARM Limited
- Mudit Bhargava
- G11 - INFORMATION STORAGE
Information Patent Grant
Read assist circuitry for memory applications
- Patent number 11,475,944
- Issue date Oct 18, 2022
- ARM Limited
- Rahul Mathur
- G11 - INFORMATION STORAGE
Information Patent Grant
3D storage architecture with tier-specific controls
- Patent number 11,468,945
- Issue date Oct 11, 2022
- ARM Limited
- Rahul Mathur
- G11 - INFORMATION STORAGE
Information Patent Grant
CAM device with 3D CAM cells
- Patent number 11,211,111
- Issue date Dec 28, 2021
- ARM Limited
- Rahul Mathur
- G11 - INFORMATION STORAGE
Information Patent Grant
Selective clock adjustment during read and/or write memory operations
- Patent number 10,896,707
- Issue date Jan 19, 2021
- ARM Limited
- Andy Wangkun Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Read assist circuitry for memory applications
- Patent number 10,854,280
- Issue date Dec 1, 2020
- ARM Limited
- Abhairaj Singh
- G11 - INFORMATION STORAGE
Information Patent Grant
Redundancy circuitry for memory application
- Patent number 10,839,934
- Issue date Nov 17, 2020
- ARM Limited
- Rahul Mathur
- G11 - INFORMATION STORAGE
Information Patent Grant
Level shifter with bypass
- Patent number 10,535,386
- Issue date Jan 14, 2020
- ARM Limited
- Andy Wangkun Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuitry for tracking bias voltage behavior
- Patent number 10,497,414
- Issue date Dec 3, 2019
- ARM Limited
- Rahul Mathur
- G11 - INFORMATION STORAGE
Information Patent Grant
Clock generation circuitry for memory applications
- Patent number 10,008,260
- Issue date Jun 26, 2018
- ARM Limited
- Bikas Maiti
- G11 - INFORMATION STORAGE
Information Patent Grant
Write assist circuitry
- Patent number 9,997,217
- Issue date Jun 12, 2018
- ARM Limited
- Ankur Goel
- G11 - INFORMATION STORAGE
Information Patent Grant
Retention voltages for integrated circuits
- Patent number 9,620,200
- Issue date Apr 11, 2017
- ARM Limited
- Sanjay Mangal
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Clock Circuitry for Memory Applications
- Publication number 20240290363
- Publication date Aug 29, 2024
- ARM Limited
- Rahul Mathur
- G11 - INFORMATION STORAGE
Information Patent Application
Burst Read with Flexible Burst Length for On-Chip Memory
- Publication number 20240055047
- Publication date Feb 15, 2024
- ARM Limited
- Edward Martin McCombs
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS AND APPARATUS FOR WORKLOAD SCHEDULING
- Publication number 20240036923
- Publication date Feb 1, 2024
- ARM Limited
- Rishav ROY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Buried Metal Techniques
- Publication number 20240038297
- Publication date Feb 1, 2024
- ARM Limited
- Rahul Mathur
- G11 - INFORMATION STORAGE
Information Patent Application
Power-Up Header Circuitry for Multi-Bank Memory
- Publication number 20240005983
- Publication date Jan 4, 2024
- ARM Limited
- Rahul Mathur
- G11 - INFORMATION STORAGE
Information Patent Application
Bitline Precharge Techniques
- Publication number 20230402092
- Publication date Dec 14, 2023
- ARM Limited
- Rahul Mathur
- G11 - INFORMATION STORAGE
Information Patent Application
TSV Coupled Integrated Circuits and Methods
- Publication number 20230178538
- Publication date Jun 8, 2023
- ARM Limited
- Rahul Mathur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and Circuits of Spatial Alignment
- Publication number 20220391469
- Publication date Dec 8, 2022
- ARM Limited
- Supreet Jeloka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multi-Tier Memory Architecture
- Publication number 20220343970
- Publication date Oct 27, 2022
- ARM Limited
- Rahul Mathur
- G11 - INFORMATION STORAGE
Information Patent Application
Circuitry Apportioning of an Integrated Circuit
- Publication number 20220246206
- Publication date Aug 4, 2022
- ARM Limited
- Mudit Bhargava
- G11 - INFORMATION STORAGE
Information Patent Application
Multi-Tier Memory Architecture
- Publication number 20220199125
- Publication date Jun 23, 2022
- ARM Limited
- Supreet Jeloka
- G11 - INFORMATION STORAGE
Information Patent Application
TSV Coupled Integrated Circuits and Methods
- Publication number 20220130816
- Publication date Apr 28, 2022
- ARM Limited
- Rahul Mathur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
3D STORAGE ARCHITECTURE WITH TIER-SPECIFIC CONTROLS
- Publication number 20220122655
- Publication date Apr 21, 2022
- ARM Limited
- Rahul Mathur
- G11 - INFORMATION STORAGE
Information Patent Application
Read Assist Circuitry for Memory Applications
- Publication number 20210082496
- Publication date Mar 18, 2021
- ARM Limited
- Rahul Mathur
- G11 - INFORMATION STORAGE
Information Patent Application
Selective Clock Adjustment During Read and/or Write Memory Operations
- Publication number 20200194047
- Publication date Jun 18, 2020
- ARM Limited
- Andy Wangkun Chen
- G11 - INFORMATION STORAGE
Information Patent Application
CIRCUITRY FOR TRACKING BIAS VOLTAGE BEHAVIOR
- Publication number 20190378550
- Publication date Dec 12, 2019
- ARM Limited
- Rahul Mathur
- G11 - INFORMATION STORAGE
Information Patent Application
Redundancy Circuitry for Memory Application
- Publication number 20190371424
- Publication date Dec 5, 2019
- ARM Limited
- Rahul Mathur
- G11 - INFORMATION STORAGE
Information Patent Application
Read Assist Circuitry for Memory Applications
- Publication number 20190066772
- Publication date Feb 28, 2019
- ARM Limited
- Abhairaj Singh
- G11 - INFORMATION STORAGE
Information Patent Application
Level Shifter with Bypass
- Publication number 20180342271
- Publication date Nov 29, 2018
- ARM Limited
- Andy Wangkun Chen
- G11 - INFORMATION STORAGE

Rahul Mathur

Person

Patents Grantslast 30 patents

Burst read with flexible burst length for on-chip memory

Power-up header circuitry for multi-bank memory

Multi-tier memory architecture

Multi-tier memory architecture

TSV coupled integrated circuits and methods

Circuitry apportioning of an integrated circuit

Read assist circuitry for memory applications

3D storage architecture with tier-specific controls

CAM device with 3D CAM cells

Selective clock adjustment during read and/or write memory operations

Read assist circuitry for memory applications

Redundancy circuitry for memory application

Level shifter with bypass

Circuitry for tracking bias voltage behavior

Clock generation circuitry for memory applications

Write assist circuitry

Retention voltages for integrated circuits

Patents Applicationslast 30 patents

Clock Circuitry for Memory Applications

Burst Read with Flexible Burst Length for On-Chip Memory

METHODS AND APPARATUS FOR WORKLOAD SCHEDULING

Buried Metal Techniques

Power-Up Header Circuitry for Multi-Bank Memory

Bitline Precharge Techniques

TSV Coupled Integrated Circuits and Methods

Methods and Circuits of Spatial Alignment

Multi-Tier Memory Architecture

Circuitry Apportioning of an Integrated Circuit

Multi-Tier Memory Architecture

TSV Coupled Integrated Circuits and Methods

3D STORAGE ARCHITECTURE WITH TIER-SPECIFIC CONTROLS

Read Assist Circuitry for Memory Applications

Selective Clock Adjustment During Read and/or Write Memory Operations

CIRCUITRY FOR TRACKING BIAS VOLTAGE BEHAVIOR

Redundancy Circuitry for Memory Application

Read Assist Circuitry for Memory Applications

Level Shifter with Bypass