Raja V.S. Halaharivi

Person

Gilroy, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Balancing performance between interface ports in a memory sub-system
- Patent number 12,086,412
- Issue date Sep 10, 2024
- Micron Technology, Inc.
- Raja V. S. Halaharivi
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
PAGE REQUEST INTERFACE SUPPORT IN HANDLING DIRECT MEMORY ACCESS WIT...
- Publication number 20240411700
- Publication date Dec 12, 2024
- Micron Technology, Inc.
- Raja V. S. Halaharivi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PAGE REQUEST INTERFACE SUPPORT IN HANDLING POINTER FETCH WITH CACHI...
- Publication number 20240411704
- Publication date Dec 12, 2024
- Micron Technology, Inc.
- Raja V. S. Halaharivi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BALANCING PERFORMANCE BETWEEN INTERFACE PORTS IN A MEMORY SUB-SYSTEM
- Publication number 20240385750
- Publication date Nov 21, 2024
- Micron Technology, Inc.
- Raja V.S. Halaharivi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGING WRITE COMMAND EXECUTION DURING A POWER FAILURE IN A MEMORY...
- Publication number 20240319873
- Publication date Sep 26, 2024
- Micron Technology, Inc.
- Raja V.S. Halaharivi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE ACTIVE COMMAND TRACKING
- Publication number 20240192891
- Publication date Jun 13, 2024
- Micron Technology, Inc.
- Horia C. Simionescu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGING NAMESPACE MAPPING, TRUSTED COMPUTING GROUP RANGES, AND ENC...
- Publication number 20240184710
- Publication date Jun 6, 2024
- Micron Technology, Inc.
- Raja V.S. Halaharivi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PAGE REQUEST INTERFACE SUPPORT IN HANDLING HOST SUBMISSION QUEUES A...
- Publication number 20240168891
- Publication date May 23, 2024
- Micron Technology, Inc.
- Prateek Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PAGE REQUEST INTERFACE SUPPORT IN CACHING HOST MEMORY ADDRESS TRANS...
- Publication number 20240160577
- Publication date May 16, 2024
- Micron Technology, Inc.
- Raja V. S. Halaharivi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
QUALITY OF SERVICE MANAGEMENT IN A MEMORY SUB-SYSTEM
- Publication number 20240160553
- Publication date May 16, 2024
- Micron Technology, Inc.
- Raja V.S. Halaharivi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHING HOST MEMORY ADDRESS TRANSLATION DATA IN A MEMORY SUB-SYSTEM
- Publication number 20240143515
- Publication date May 2, 2024
- Micron Technology, Inc.
- Sumangal Chakrabarty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BALANCING PERFORMANCE BETWEEN INTERFACE PORTS IN A MEMORY SUB-SYSTEM
- Publication number 20240069732
- Publication date Feb 29, 2024
- Micron Technology, Inc.
- Raja V.S. Halaharivi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGING COMMAND COMPLETION NOTIFICATION PACING IN A MEMORY SUB-SYSTEM
- Publication number 20240069807
- Publication date Feb 29, 2024
- Micron Technology, Inc.
- Raja V.S. Halaharivi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
READ OPERATIONS FOR MIXED DATA
- Publication number 20240069771
- Publication date Feb 29, 2024
- Micron Technology, Inc.
- Scheheresade VIRANI
- G06 - COMPUTING CALCULATING COUNTING

Raja V.S. Halaharivi

Person

Patents Grantslast 30 patents

Balancing performance between interface ports in a memory sub-system

Patents Applicationslast 30 patents

PAGE REQUEST INTERFACE SUPPORT IN HANDLING DIRECT MEMORY ACCESS WIT...

PAGE REQUEST INTERFACE SUPPORT IN HANDLING POINTER FETCH WITH CACHI...

BALANCING PERFORMANCE BETWEEN INTERFACE PORTS IN A MEMORY SUB-SYSTEM

MANAGING WRITE COMMAND EXECUTION DURING A POWER FAILURE IN A MEMORY...

MEMORY DEVICE ACTIVE COMMAND TRACKING

MANAGING NAMESPACE MAPPING, TRUSTED COMPUTING GROUP RANGES, AND ENC...

PAGE REQUEST INTERFACE SUPPORT IN HANDLING HOST SUBMISSION QUEUES A...

PAGE REQUEST INTERFACE SUPPORT IN CACHING HOST MEMORY ADDRESS TRANS...

QUALITY OF SERVICE MANAGEMENT IN A MEMORY SUB-SYSTEM

CACHING HOST MEMORY ADDRESS TRANSLATION DATA IN A MEMORY SUB-SYSTEM

BALANCING PERFORMANCE BETWEEN INTERFACE PORTS IN A MEMORY SUB-SYSTEM

MANAGING COMMAND COMPLETION NOTIFICATION PACING IN A MEMORY SUB-SYSTEM

READ OPERATIONS FOR MIXED DATA