Rajasekaran Swaminathan

Person

Tempe, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Pitch translation architecture for semiconductor package including...
- Patent number 12,051,647
- Issue date Jul 30, 2024
- Intel Corporation
- Andrew Collins
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
BGA STIM package architecture for high performance systems
- Patent number 11,817,364
- Issue date Nov 14, 2023
- Intel Corporation
- Rajasekaran Swaminathan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multiple die package using an embedded bridge connecting dies
- Patent number 11,742,293
- Issue date Aug 29, 2023
- Intel Corporation
- Yidnekachew S. Mekonnen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Pitch translation architecture for semiconductor package including...
- Patent number 11,705,398
- Issue date Jul 18, 2023
- Intel Corporation
- Andrew Collins
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ultra-thin, hyper-density semiconductor packages
- Patent number 11,430,724
- Issue date Aug 30, 2022
- Intel Corporation
- Debendra Mallik
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip with magnetic interconnect alignment
- Patent number 11,296,050
- Issue date Apr 5, 2022
- Intel Corporation
- Rajasekaran Swaminathan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Pitch translation architecture for semiconductor package including...
- Patent number 11,270,942
- Issue date Mar 8, 2022
- Intel Corporation
- Andrew Collins
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Rlink—die to die channel interconnect configurations to improve sig...
- Patent number 10,784,204
- Issue date Sep 22, 2020
- Intel Corporation
- Kemal Aygun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Pitch translation architecture for semiconductor package including...
- Patent number 10,643,945
- Issue date May 5, 2020
- Intel Corporation
- Andrew Collins
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Printed circuit board with a recess to accommodate discrete compone...
- Patent number 10,187,996
- Issue date Jan 22, 2019
- Intel Corporation
- Rajasekaran Swaminathan
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Interconnect cable with edge finger connector
- Patent number 10,074,920
- Issue date Sep 11, 2018
- Intel Corporation
- Donald T. Tran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Magnetic intermetallic compound interconnect
- Patent number 9,847,308
- Issue date Dec 19, 2017
- Intel Corporation
- Rajasekaran Swaminathan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CPU package substrates with removable memory mechanical interfaces
- Patent number 9,832,876
- Issue date Nov 28, 2017
- Intel Corporation
- Mani Prakash
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Forming sacrificial composite materials for package-on-package arch...
- Patent number 9,793,233
- Issue date Oct 17, 2017
- Intel Corporation
- Rajasekaran Swaminathan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip package connector assembly
- Patent number 9,674,954
- Issue date Jun 6, 2017
- Intel Corporation
- Rajasekaran Swaminathan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Techniques and configurations associated with a package load assembly
- Patent number 9,615,483
- Issue date Apr 4, 2017
- Intel Corporation
- Gaurav Chawla
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electronic package with narrow-factor via including finish layer
- Patent number 9,603,247
- Issue date Mar 21, 2017
- Intel Corporation
- Rajasekaran Swaminathan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Double-mated edge finger connector
- Patent number 9,502,800
- Issue date Nov 22, 2016
- Intel Corporation
- Donald T. Tran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Snap connector for socket assembly and associated techniques and co...
- Patent number 9,478,881
- Issue date Oct 25, 2016
- Intel Corporation
- Zhichao Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Forming sacrificial composite materials for package-on-package arch...
- Patent number 9,472,519
- Issue date Oct 18, 2016
- Intel Corporation
- Rajasekaran Swaminathan
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Methods of forming ultra thin package structures including low temp...
- Patent number 9,461,014
- Issue date Oct 4, 2016
- Intel Corporation
- Sriram Srinivasan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit connectors
- Patent number 9,265,170
- Issue date Feb 16, 2016
- Intel Corporation
- Rajasekaran Swaminathan
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Interconnect cable with edge finger connector
- Patent number 9,118,151
- Issue date Aug 25, 2015
- Intel Corporation
- Donald T. Tran
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Methods of forming ultra thin package structures including low temp...
- Patent number 9,064,971
- Issue date Jun 23, 2015
- Intel Corporation
- Sriram Srinivasan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Magnetic attachment structure
- Patent number 9,010,618
- Issue date Apr 21, 2015
- Intel Corporation
- Aleksandar Aleksov
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Forming sacrificial composite materials for package-on-package arch...
- Patent number 9,006,887
- Issue date Apr 14, 2015
- Intel Corporation
- Rajasekaran Swaminathan
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Magnetic intermetallic compound interconnect
- Patent number 8,939,347
- Issue date Jan 27, 2015
- Intel Corporation
- Rajasekaran Swaminathan
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Connector assembly with integrated pitch translation
- Patent number 8,915,747
- Issue date Dec 23, 2014
- Intel Corporation
- Gaurav Chawla
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Magnetically sintered conductive via
- Patent number 8,609,532
- Issue date Dec 17, 2013
- Intel Corporation
- Rajasekaran Swaminathan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Coating for a microelectronic device, treatment comprising same, an...
- Patent number 8,569,108
- Issue date Oct 29, 2013
- Intel Corporation
- Dingying Xu
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC

Patents Applicationslast 30 patents

Information Patent Application
PITCH TRANSLATION ARCHITECTURE FOR SEMICONDUCTOR PACKAGE INCLUDING...
- Publication number 20240347457
- Publication date Oct 17, 2024
- Intel Corporation
- Andrew COLLINS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BGA STIM PACKAGE ARCHITECTURE FOR HIGH PERFORMANCE SYSTEMS
- Publication number 20240030086
- Publication date Jan 25, 2024
- Intel Corporation
- Rajasekaran SWAMINATHAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ULTRA-THIN, HYPER-DENSITY SEMICONDUCTOR PACKAGES
- Publication number 20240030116
- Publication date Jan 25, 2024
- Intel Corporation
- Debendra MALLIK
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTIPLE DIE PACKAGE USING AN EMBEDDED BRIDGE CONNECTING DIES
- Publication number 20230352412
- Publication date Nov 2, 2023
- Intel Corporation
- Yidnekachew S. MEKONNEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PITCH TRANSLATION ARCHITECTURE FOR SEMICONDUCTOR PACKAGE INCLUDING...
- Publication number 20230290728
- Publication date Sep 14, 2023
- Intel Corporation
- Andrew COLLINS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ULTRA-THIN, HYPER-DENSITY SEMICONDUCTOR PACKAGES
- Publication number 20230138543
- Publication date May 4, 2023
- Intel Corporation
- Debendra MALLIK
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ULTRA-THIN, HYPER-DENSITY SEMICONDUCTOR PACKAGES
- Publication number 20220344247
- Publication date Oct 27, 2022
- Intel Corporation
- Debendra MALLIK
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PITCH TRANSLATION ARCHITECTURE FOR SEMICONDUCTOR PACKAGE INCLUDING...
- Publication number 20220148968
- Publication date May 12, 2022
- Intel Corporation
- Andrew COLLINS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP WITH MAGNETIC INTERCONNECT ALIGNMENT
- Publication number 20210066240
- Publication date Mar 4, 2021
- Intel Corporation
- Rajasekaran Swaminathan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ULTRA-THIN, HYPER-DENSITY SEMICONDUCTOR PACKAGES
- Publication number 20200273784
- Publication date Aug 27, 2020
- Intel Corporation
- Debendra MALLIK
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PITCH TRANSLATION ARCHITECTURE FOR SEMICONDUCTOR PACKAGE INCLUDING...
- Publication number 20200235051
- Publication date Jul 23, 2020
- Intel Corporation
- Andrew COLLINS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RLINK - DIE TO DIE CHANNEL INTERCONNECT CONFIGURATIONS TO IMPROVE S...
- Publication number 20200066641
- Publication date Feb 27, 2020
- Intel Corporation
- Kemal AYGUN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BGA STIM PACKAGE ARCHITECTURE FOR HIGH PERFORMANCE SYSTEMS
- Publication number 20190393121
- Publication date Dec 26, 2019
- Rajasekaran SWAMINATHAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTIPLE DIE PACKAGE USING AN EMBEDDED BRIDGE CONNECTING DIES
- Publication number 20190363049
- Publication date Nov 28, 2019
- Intel Corporation
- Yidnekachew S. MEKONNEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PITCH TRANSLATION ARCHITECTURE FOR SEMICONDUCTOR PACKAGE INCLUDING...
- Publication number 20190206792
- Publication date Jul 4, 2019
- Andrew Collins
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PRINTED CIRCUIT BOARD WITH A RECESS TO ACCOMMODATE DISCRETE COMPONE...
- Publication number 20180270957
- Publication date Sep 20, 2018
- Intel Corporation
- Rajasekaran Swaminathan
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
CPU PACKAGE SUBSTRATES WITH REMOVABLE MEMORY MECHANICAL INTERFACES
- Publication number 20180007791
- Publication date Jan 4, 2018
- Intel Corporation
- Mani Prakash
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MAGNETIC INTERMETALLIC COMPOUND INTERCONNECT
- Publication number 20160379951
- Publication date Dec 29, 2016
- Intel Corporation
- RAJASEKARAN SWAMINATHAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORMING SACRIFICIAL COMPOSITE MATERIALS FOR PACKAGE-ON-PACKAGE ARCH...
- Publication number 20160343680
- Publication date Nov 24, 2016
- Intel Corporation
- Rajasekaran SWAMINATHAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SNAP CONNECTOR FOR SOCKET ASSEMBLY AND ASSOCIATED TECHNIQUES AND CO...
- Publication number 20160268710
- Publication date Sep 15, 2016
- Intel Corporation
- Zhichao Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CPU PACKAGE SUBSTRATES WITH REMOVABLE MEMORY MECHANICAL INTERFACES
- Publication number 20160183374
- Publication date Jun 23, 2016
- Mani Prakash
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MAGNETIC INTERMETALLIC COMPOUND INTERCONNECT
- Publication number 20160172320
- Publication date Jun 16, 2016
- Intel Corporation
- RAJASEKARAN SWAMINATHAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES AND CONFIGURATIONS ASSOCIATED WITH A PACKAGE LOAD ASSEMBLY
- Publication number 20160079150
- Publication date Mar 17, 2016
- Intel Corporation
- Gaurav Chawla
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
ELECTRONIC PACKAGE WITH NARROW-FACTOR VIA INCLUDING FINISH LAYER
- Publication number 20160044786
- Publication date Feb 11, 2016
- Rajasekaran Swaminathan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERCONNECT CABLE WITH EDGE FINGER CONNECTOR
- Publication number 20150357736
- Publication date Dec 10, 2015
- Intel Corporation
- Donald T. Tran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DOUBLE-MATED EDGE FINGER CONNECTOR
- Publication number 20150318630
- Publication date Nov 5, 2015
- Donald T. Tran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING ULTRA THIN PACKAGE STRUCTURES INCLUDING LOW TEMP...
- Publication number 20150221609
- Publication date Aug 6, 2015
- Intel Corporation
- Sriram Srinivasan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORMING SACRIFICIAL COMPOSITE MATERIALS FOR PACKAGE-ON-PACKAGE ARCH...
- Publication number 20150194401
- Publication date Jul 9, 2015
- Intel Corporation
- Rajasekaran SWAMINATHAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT CONNECTORS
- Publication number 20150118870
- Publication date Apr 30, 2015
- Rajasekaran Swaminathan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERCONNECT CABLE WITH EDGE FINGER CONNECTOR
- Publication number 20140322932
- Publication date Oct 30, 2014
- Donald T. Tran
- H01 - BASIC ELECTRIC ELEMENTS

Rajasekaran Swaminathan

Person

Patents Grantslast 30 patents

Pitch translation architecture for semiconductor package including...

BGA STIM package architecture for high performance systems

Multiple die package using an embedded bridge connecting dies

Pitch translation architecture for semiconductor package including...

Ultra-thin, hyper-density semiconductor packages

Chip with magnetic interconnect alignment

Pitch translation architecture for semiconductor package including...

Rlink—die to die channel interconnect configurations to improve sig...

Pitch translation architecture for semiconductor package including...

Printed circuit board with a recess to accommodate discrete compone...

Interconnect cable with edge finger connector

Magnetic intermetallic compound interconnect

CPU package substrates with removable memory mechanical interfaces

Forming sacrificial composite materials for package-on-package arch...

Chip package connector assembly

Techniques and configurations associated with a package load assembly

Electronic package with narrow-factor via including finish layer

Double-mated edge finger connector

Snap connector for socket assembly and associated techniques and co...

Forming sacrificial composite materials for package-on-package arch...

Methods of forming ultra thin package structures including low temp...

Integrated circuit connectors

Interconnect cable with edge finger connector

Methods of forming ultra thin package structures including low temp...

Magnetic attachment structure

Forming sacrificial composite materials for package-on-package arch...

Magnetic intermetallic compound interconnect

Connector assembly with integrated pitch translation

Magnetically sintered conductive via

Coating for a microelectronic device, treatment comprising same, an...

Patents Applicationslast 30 patents

PITCH TRANSLATION ARCHITECTURE FOR SEMICONDUCTOR PACKAGE INCLUDING...

BGA STIM PACKAGE ARCHITECTURE FOR HIGH PERFORMANCE SYSTEMS

ULTRA-THIN, HYPER-DENSITY SEMICONDUCTOR PACKAGES

MULTIPLE DIE PACKAGE USING AN EMBEDDED BRIDGE CONNECTING DIES

PITCH TRANSLATION ARCHITECTURE FOR SEMICONDUCTOR PACKAGE INCLUDING...

ULTRA-THIN, HYPER-DENSITY SEMICONDUCTOR PACKAGES

ULTRA-THIN, HYPER-DENSITY SEMICONDUCTOR PACKAGES

PITCH TRANSLATION ARCHITECTURE FOR SEMICONDUCTOR PACKAGE INCLUDING...

CHIP WITH MAGNETIC INTERCONNECT ALIGNMENT

ULTRA-THIN, HYPER-DENSITY SEMICONDUCTOR PACKAGES

PITCH TRANSLATION ARCHITECTURE FOR SEMICONDUCTOR PACKAGE INCLUDING...

RLINK - DIE TO DIE CHANNEL INTERCONNECT CONFIGURATIONS TO IMPROVE S...

BGA STIM PACKAGE ARCHITECTURE FOR HIGH PERFORMANCE SYSTEMS

MULTIPLE DIE PACKAGE USING AN EMBEDDED BRIDGE CONNECTING DIES

PITCH TRANSLATION ARCHITECTURE FOR SEMICONDUCTOR PACKAGE INCLUDING...

PRINTED CIRCUIT BOARD WITH A RECESS TO ACCOMMODATE DISCRETE COMPONE...

CPU PACKAGE SUBSTRATES WITH REMOVABLE MEMORY MECHANICAL INTERFACES

MAGNETIC INTERMETALLIC COMPOUND INTERCONNECT

FORMING SACRIFICIAL COMPOSITE MATERIALS FOR PACKAGE-ON-PACKAGE ARCH...

SNAP CONNECTOR FOR SOCKET ASSEMBLY AND ASSOCIATED TECHNIQUES AND CO...

CPU PACKAGE SUBSTRATES WITH REMOVABLE MEMORY MECHANICAL INTERFACES

MAGNETIC INTERMETALLIC COMPOUND INTERCONNECT

TECHNIQUES AND CONFIGURATIONS ASSOCIATED WITH A PACKAGE LOAD ASSEMBLY

ELECTRONIC PACKAGE WITH NARROW-FACTOR VIA INCLUDING FINISH LAYER

INTERCONNECT CABLE WITH EDGE FINGER CONNECTOR

DOUBLE-MATED EDGE FINGER CONNECTOR

METHODS OF FORMING ULTRA THIN PACKAGE STRUCTURES INCLUDING LOW TEMP...

FORMING SACRIFICIAL COMPOSITE MATERIALS FOR PACKAGE-ON-PACKAGE ARCH...

INTEGRATED CIRCUIT CONNECTORS

INTERCONNECT CABLE WITH EDGE FINGER CONNECTOR