Rajeev D. Joshi

Person

Cupertino, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Integration of a passive component in a cavity of an integrated cir...
- Patent number 11,430,722
- Issue date Aug 30, 2022
- Texas Instruments Incorporated
- Jeffrey Morroni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package with integrated passive electrical component
- Patent number 11,257,739
- Issue date Feb 22, 2022
- Texas Instruments Incorporated
- Joyce Marie Mullenix
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integration of a passive component in an integrated circuit package
- Patent number 10,734,313
- Issue date Aug 4, 2020
- Texas Instruments Incorporated
- Jeffrey Morroni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package with integrated passive electrical component
- Patent number 10,714,412
- Issue date Jul 14, 2020
- Texas Instruments Incorporated
- Joyce Marie Mullenix
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor systems having dual leadframes
- Patent number 10,573,582
- Issue date Feb 25, 2020
- Texas Instruments Incorporated
- Rajeev D. Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor systems having premolded dual leadframes
- Patent number 10,312,184
- Issue date Jun 4, 2019
- Texas Instruments Incorporated
- Rajeev D. Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Power module with improved cooling and method for making
- Patent number 9,468,087
- Issue date Oct 11, 2016
- Texas Instruments Incorporated
- Rajeev Dinkar Joshi
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Converter having partially thinned leadframe with stacked chips and...
- Patent number 9,355,946
- Issue date May 31, 2016
- Texas Instruments Incorporated
- Rajeev Dinkar Joshi
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Semiconductor die package and method for making the same
- Patent number 9,159,656
- Issue date Oct 13, 2015
- Fairchild Semiconductor Corporation
- Oseob Jeon
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Converter having partially thinned leadframe with stacked chips and...
- Patent number 9,136,256
- Issue date Sep 15, 2015
- Texas Instruments Incorporated
- Rajeev Dinkar Joshi
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Method of forming a magnetics package
- Patent number 9,053,853
- Issue date Jun 9, 2015
- Flextronics AP, LLC
- Rajeev Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
DC/DC converter power module package incorporating a stacked contro...
- Patent number 8,679,896
- Issue date Mar 25, 2014
- National Semiconductor Corporation
- Rajeev Joshi
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Semiconductor die package and method for making the same
- Patent number 8,664,752
- Issue date Mar 4, 2014
- Fairchild Semiconductor Corporation
- Oseob Jeon
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Leadframe based photo voltaic electronic assembly
- Patent number 8,609,978
- Issue date Dec 17, 2013
- Flextronics AP, LLC
- Rajeev Joshi
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Substrate based unmolded package
- Patent number 8,541,890
- Issue date Sep 24, 2013
- Fairchild Semiconductor Corporation
- Rajeev Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package including an embedded power stage wherei...
- Patent number 8,524,532
- Issue date Sep 3, 2013
- Texas Instruments Incorporated
- Rajeev Joshi
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Leadframe based magnetics package
- Patent number 8,339,231
- Issue date Dec 25, 2012
- Flextronics AP, LLC
- Rajeev Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thermal enhanced upper and dual heat sink exposed molded leadless p...
- Patent number 8,278,742
- Issue date Oct 2, 2012
- Fairchild Semiconductor Corporation
- Chung-Lin Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor die package including multiple dies and a common node...
- Patent number 8,212,361
- Issue date Jul 3, 2012
- Fairchild Semiconductor Corporation
- Rajeev Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor die package and method for making the same
- Patent number 8,183,088
- Issue date May 22, 2012
- Fairchild Semiconductor Corporation
- Oseob Jeon
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Method of providing a RF shield of an electronic device
- Patent number 7,971,350
- Issue date Jul 5, 2011
- Flextronics AP, LLC
- Rajeev Joshi
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Thermal enhanced upper and dual heat sink exposed molded leadless p...
- Patent number 7,968,982
- Issue date Jun 28, 2011
- Fairchild Semiconductor Corporation
- Chung-Lin Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual metal stud bumping for flip chip applications
- Patent number 7,932,171
- Issue date Apr 26, 2011
- Fairchild Semiconductor Corporation
- Rajeev Joshi
- A61 - MEDICAL OR VETERINARY SCIENCE HYGIENE
Information Patent Grant
High performance multi-chip flip chip package
- Patent number 7,892,884
- Issue date Feb 22, 2011
- Fairchild Semiconductor Corporation
- Rajeev Joshi
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Integrated transistor module and method of fabricating same
- Patent number 7,842,555
- Issue date Nov 30, 2010
- Fairchild Semiconductor Corporation
- Rajeev D. Joshi
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Thin, thermally enhanced flip chip in a leaded molded package
- Patent number 7,821,124
- Issue date Oct 26, 2010
- Fairchild Semiconductor Corporation
- Rajeev Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Substrate based unmolded package
- Patent number 7,790,513
- Issue date Sep 7, 2010
- Fairchild Semiconductor Corporation
- Rajeev Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor die package and method for making the same
- Patent number 7,772,681
- Issue date Aug 10, 2010
- Fairchild Semiconductor Corporation
- Rajeev Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Substrate based unmolded package
- Patent number 7,682,877
- Issue date Mar 23, 2010
- Fairchild Semiconductor Corporation
- Rajeev Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer-level chip scale package and method for fabricating and using...
- Patent number 7,632,719
- Issue date Dec 15, 2009
- Fairchild Korea Semiconductor, Ltd.
- Seung Yong Choi
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATION OF A PASSIVE COMPONENT IN A CAVITY OF AN INTEGRATED CIR...
- Publication number 20220415768
- Publication date Dec 29, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Jeffrey MORRONI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE WITH INTEGRATED PASSIVE ELECTRICAL COMPONENT
- Publication number 20200343164
- Publication date Oct 29, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Joyce Marie MULLENIX
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Systems Having Premolded Dual Leadframes
- Publication number 20190237395
- Publication date Aug 1, 2019
- TEXAS INSTRUMENTS INCORPORATED
- Rajeev D. Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE WITH INTEGRATED PASSIVE ELECTRICAL COMPONENT
- Publication number 20190157188
- Publication date May 23, 2019
- TEXAS INSTRUMENTS INCORPORATED
- Joyce Marie MULLENIX
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATION OF A PASSIVE COMPONENT IN A CAVITY OF AN INTEGRATED CIR...
- Publication number 20180301402
- Publication date Oct 18, 2018
- TEXAS INSTRUMENTS INCORPORATED
- Jeffrey MORRONI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATION OF A PASSIVE COMPONENT IN A CAVITY OF AN INTEGRATED CIR...
- Publication number 20180301403
- Publication date Oct 18, 2018
- TEXAS INSTRUMENTS INCORPORATED
- Jeffrey MORRONI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATION OF A PASSIVE COMPONENT IN AN INTEGRATED CIRCUIT PACKAGE
- Publication number 20180301404
- Publication date Oct 18, 2018
- TEXAS INSTRUMENTS INCORPORATED
- Jeffrey MORRONI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Systems Having Premolded Dual Leadframes
- Publication number 20170125324
- Publication date May 4, 2017
- TEXAS INSTRUMENTS INCORPORATED
- Rajeev D. Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONVERTER HAVING PARTIALLY THINNED LEADFRAME WITH STACKED CHIPS AND...
- Publication number 20150348890
- Publication date Dec 3, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Rajeev Dinkar Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONVERTER HAVING PARTIALLY THINNED LEADFRAME WITH STACKED CHIPS AND...
- Publication number 20150235999
- Publication date Aug 20, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Rajeev Dinkar Joshi
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
SEMICONDUCTOR DIE PACKAGE AND METHOD FOR MAKING THE SAME
- Publication number 20140167238
- Publication date Jun 19, 2014
- Fairchild Semiconductor Corporation
- Oseob Jeon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EMBEDDED POWER STAGE MODULE
- Publication number 20130221442
- Publication date Aug 29, 2013
- TEXAS INSTRUMENTS INCORPORATED
- Rajeev JOSHI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DC/DC Converter Power Module Package Incorporating a Stacked Contro...
- Publication number 20130214399
- Publication date Aug 22, 2013
- National Semiconductor Corporation
- Rajeev Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DC/DC CONVERTOR POWER MODULE PACKAGE INCORPORATING A STACKED CONTRO...
- Publication number 20120326287
- Publication date Dec 27, 2012
- National Semiconductor Corporation
- Rajeev Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DIE PACKAGE AND METHOD FOR MAKING THE SAME
- Publication number 20120181675
- Publication date Jul 19, 2012
- Oseob Jeon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DIE PACKAGE INCLUDING MULTIPLE DIES AND A COMMON NODE...
- Publication number 20120064667
- Publication date Mar 15, 2012
- Rajeev Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THERMAL ENHANCED UPPER AND DUAL HEAT SINK EXPOSED MOLDED LEADLESS P...
- Publication number 20110124158
- Publication date May 26, 2011
- Fairchild Semiconductor Corporation
- Chung-Lin Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DIE PACKAGE AND METHOD FOR MAKING THE SAME
- Publication number 20100258925
- Publication date Oct 14, 2010
- Oseob Jeon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DIE PACKAGE INCLUDING MULTIPLE DIES AND A COMMON NODE...
- Publication number 20100090331
- Publication date Apr 15, 2010
- Rajeev Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH PERFORMANCE MULTI-CHIP FLIP CHIP PACKAGE
- Publication number 20090230540
- Publication date Sep 17, 2009
- Rajeev Joshi
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
DUAL METAL STUD BUMPING FOR FLIP CHIP APPLICATIONS
- Publication number 20090186452
- Publication date Jul 23, 2009
- Rajeev Joshi
- A61 - MEDICAL OR VETERINARY SCIENCE HYGIENE
Information Patent Application
SUBSTRATE BASED UNMOLDED PACKAGE
- Publication number 20090130802
- Publication date May 21, 2009
- Rajeev Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED TRANSISTOR MODULE AND METHOD OF FABRICATING SAME
- Publication number 20090117690
- Publication date May 7, 2009
- Rajeev D. Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER-LEVEL CHIP SCALE PACKAGE AND METHOD FOR FABRICATING AND USING...
- Publication number 20090111219
- Publication date Apr 30, 2009
- Seung-Yong Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THERMAL ENHANCED UPPER AND DUAL HEAT SINK EXPOSED MOLDED LEADLESS P...
- Publication number 20090072362
- Publication date Mar 19, 2009
- Fairchild Semiconductor Corporation
- Chung-Lin Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of and apparatus for providing an RF shield on an electronic...
- Publication number 20090032300
- Publication date Feb 5, 2009
- Flextronics AP, LLC
- Rajeev Joshi
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
SUBSTRATE BASED UNMOLDED PACKAGE
- Publication number 20080213946
- Publication date Sep 4, 2008
- Rajeev Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Leadframe based photo voltaic electronic assembly
- Publication number 20080190480
- Publication date Aug 14, 2008
- Flextronics AP, LLC
- Rajeev Joshi
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
THIN, THERMALLY ENHANCED FLIP CHIP IN A LEADED MOLDED PACKAGE
- Publication number 20080105957
- Publication date May 8, 2008
- Rajeev Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FLIP CHIP IN LEADED MOLDED PACKAGE AND METHOD OF MANUFACTURE THEREOF
- Publication number 20080036056
- Publication date Feb 14, 2008
- Rajeev Joshi
- H01 - BASIC ELECTRIC ELEMENTS

Rajeev D. Joshi

Person

Patents Grantslast 30 patents

Integration of a passive component in a cavity of an integrated cir...

Semiconductor package with integrated passive electrical component

Integration of a passive component in an integrated circuit package

Semiconductor package with integrated passive electrical component

Semiconductor systems having dual leadframes

Semiconductor systems having premolded dual leadframes

Power module with improved cooling and method for making

Converter having partially thinned leadframe with stacked chips and...

Semiconductor die package and method for making the same

Converter having partially thinned leadframe with stacked chips and...

Method of forming a magnetics package

DC/DC converter power module package incorporating a stacked contro...

Semiconductor die package and method for making the same

Leadframe based photo voltaic electronic assembly

Substrate based unmolded package

Integrated circuit package including an embedded power stage wherei...

Leadframe based magnetics package

Thermal enhanced upper and dual heat sink exposed molded leadless p...

Semiconductor die package including multiple dies and a common node...

Semiconductor die package and method for making the same

Method of providing a RF shield of an electronic device

Thermal enhanced upper and dual heat sink exposed molded leadless p...

Dual metal stud bumping for flip chip applications

High performance multi-chip flip chip package

Integrated transistor module and method of fabricating same

Thin, thermally enhanced flip chip in a leaded molded package

Substrate based unmolded package

Semiconductor die package and method for making the same

Substrate based unmolded package

Wafer-level chip scale package and method for fabricating and using...

Patents Applicationslast 30 patents

INTEGRATION OF A PASSIVE COMPONENT IN A CAVITY OF AN INTEGRATED CIR...

SEMICONDUCTOR PACKAGE WITH INTEGRATED PASSIVE ELECTRICAL COMPONENT

Semiconductor Systems Having Premolded Dual Leadframes

SEMICONDUCTOR PACKAGE WITH INTEGRATED PASSIVE ELECTRICAL COMPONENT

INTEGRATION OF A PASSIVE COMPONENT IN A CAVITY OF AN INTEGRATED CIR...

INTEGRATION OF A PASSIVE COMPONENT IN A CAVITY OF AN INTEGRATED CIR...

INTEGRATION OF A PASSIVE COMPONENT IN AN INTEGRATED CIRCUIT PACKAGE

Semiconductor Systems Having Premolded Dual Leadframes

CONVERTER HAVING PARTIALLY THINNED LEADFRAME WITH STACKED CHIPS AND...

CONVERTER HAVING PARTIALLY THINNED LEADFRAME WITH STACKED CHIPS AND...

SEMICONDUCTOR DIE PACKAGE AND METHOD FOR MAKING THE SAME

EMBEDDED POWER STAGE MODULE

DC/DC Converter Power Module Package Incorporating a Stacked Contro...

DC/DC CONVERTOR POWER MODULE PACKAGE INCORPORATING A STACKED CONTRO...

SEMICONDUCTOR DIE PACKAGE AND METHOD FOR MAKING THE SAME

SEMICONDUCTOR DIE PACKAGE INCLUDING MULTIPLE DIES AND A COMMON NODE...

THERMAL ENHANCED UPPER AND DUAL HEAT SINK EXPOSED MOLDED LEADLESS P...

SEMICONDUCTOR DIE PACKAGE AND METHOD FOR MAKING THE SAME

SEMICONDUCTOR DIE PACKAGE INCLUDING MULTIPLE DIES AND A COMMON NODE...

HIGH PERFORMANCE MULTI-CHIP FLIP CHIP PACKAGE

DUAL METAL STUD BUMPING FOR FLIP CHIP APPLICATIONS

SUBSTRATE BASED UNMOLDED PACKAGE

INTEGRATED TRANSISTOR MODULE AND METHOD OF FABRICATING SAME

WAFER-LEVEL CHIP SCALE PACKAGE AND METHOD FOR FABRICATING AND USING...

THERMAL ENHANCED UPPER AND DUAL HEAT SINK EXPOSED MOLDED LEADLESS P...

Method of and apparatus for providing an RF shield on an electronic...

SUBSTRATE BASED UNMOLDED PACKAGE

Leadframe based photo voltaic electronic assembly

THIN, THERMALLY ENHANCED FLIP CHIP IN A LEADED MOLDED PACKAGE

FLIP CHIP IN LEADED MOLDED PACKAGE AND METHOD OF MANUFACTURE THEREOF