Rajeev Murgai

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Estimating jitter in a clock tree of a circuit and synthesizing a j...
- Patent number 7,890,904
- Issue date Feb 15, 2011
- Fujitsu Limited
- Rajeev Murgai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for providing an improved sliding window scheme f...
- Patent number 7,802,215
- Issue date Sep 21, 2010
- Fujitsu Limited
- Subodh M. Reddy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Analyzing timing uncertainty in mesh-based architectures
- Patent number 7,801,718
- Issue date Sep 21, 2010
- Fujitsu Limited
- Subodh M. Reddy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Border-enhanced sliding window scheme (SWS) for determining clock t...
- Patent number 7,788,613
- Issue date Aug 31, 2010
- Fujitsu Limited
- William W. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sliding window scheme (SWS) for determining clock timing in a mesh-...
- Patent number 7,725,852
- Issue date May 25, 2010
- Fujitsu Limited
- Hongyu Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Crosstalk-aware timing analysis
- Patent number 7,383,522
- Issue date Jun 3, 2008
- Fujitsu Limited
- Rajeev Murgai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computing current in a digital circuit based on an accurate current...
- Patent number 7,313,771
- Issue date Dec 25, 2007
- Fujitsu Limited
- Subodh M. Reddy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Analyzing substrate noise
- Patent number 7,246,335
- Issue date Jul 17, 2007
- Fujitsu Limited
- Rajeev Murgai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout-driven, area-constrained design optimization
- Patent number 7,197,732
- Issue date Mar 27, 2007
- Fujitsu Limited
- Rajeev Murgai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Process for automated generation of design-specific complex functio...
- Patent number 7,003,738
- Issue date Feb 21, 2006
- Zenasis Technologies, Inc.
- Debashis Bhattacharya
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Constructing a Replica-Based Clock Tree
- Publication number 20100049481
- Publication date Feb 25, 2010
- Fujitsu Limited
- William W. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and Method for Providing an Improved Sliding Window Scheme f...
- Publication number 20070283305
- Publication date Dec 6, 2007
- Fujitsu Limited
- Subodh M. Reddy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Analyzing Timing Uncertainty in Mesh-Based Architectures
- Publication number 20070208552
- Publication date Sep 6, 2007
- FUJITSU LIMITED
- Subodh M. Reddy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Border-Enhanced Sliding Window Scheme (SWS) for Determining Clock T...
- Publication number 20070038430
- Publication date Feb 15, 2007
- William W. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Sliding Window Scheme (SWS) for Determining Clock Timing in a Mesh-...
- Publication number 20070016882
- Publication date Jan 18, 2007
- Hongyu Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Estimating Jitter In A Clock Tree Of A Circuit And Synthesizing A J...
- Publication number 20060288320
- Publication date Dec 21, 2006
- Rajeev Murgai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Computing current in a digital circuit based on an accurate current...
- Publication number 20060225009
- Publication date Oct 5, 2006
- Subodh M. Reddy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Analyzing substrate noise
- Publication number 20060184904
- Publication date Aug 17, 2006
- Rajeev Murgai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Layout-driven, area-constrained design optimization
- Publication number 20060129960
- Publication date Jun 15, 2006
- FUJITSU LIMITED
- Rajeev Murgai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Crosstalk-aware timing analysis
- Publication number 20060080627
- Publication date Apr 13, 2006
- FUJITSU LIMITED
- Rajeev Murgai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Process for automated generation of design-specific complex functio...
- Publication number 20020053063
- Publication date May 2, 2002
- Zenasis Technologies, Inc.
- Debashis Bhattacharya
- G06 - COMPUTING CALCULATING COUNTING

Rajeev Murgai

Person

Patents Grantslast 30 patents

Estimating jitter in a clock tree of a circuit and synthesizing a j...

System and method for providing an improved sliding window scheme f...

Analyzing timing uncertainty in mesh-based architectures

Border-enhanced sliding window scheme (SWS) for determining clock t...

Sliding window scheme (SWS) for determining clock timing in a mesh-...

Crosstalk-aware timing analysis

Computing current in a digital circuit based on an accurate current...

Analyzing substrate noise

Layout-driven, area-constrained design optimization

Process for automated generation of design-specific complex functio...

Patents Applicationslast 30 patents

Constructing a Replica-Based Clock Tree

System and Method for Providing an Improved Sliding Window Scheme f...

Analyzing Timing Uncertainty in Mesh-Based Architectures

Border-Enhanced Sliding Window Scheme (SWS) for Determining Clock T...

Sliding Window Scheme (SWS) for Determining Clock Timing in a Mesh-...

Estimating Jitter In A Clock Tree Of A Circuit And Synthesizing A J...

Computing current in a digital circuit based on an accurate current...

Analyzing substrate noise

Layout-driven, area-constrained design optimization

Crosstalk-aware timing analysis

Process for automated generation of design-specific complex functio...