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Rajesh Galivanche
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Saratoga, CA, US
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last 30 patents
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Patent Grant
Device, system, and method for optimized concurrent error detection
Patent number
7,861,116
Issue date
Dec 28, 2010
Intel Corporation
Abhijit Jas
G06 - COMPUTING CALCULATING COUNTING
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Patent Grant
Dft technique for avoiding contention/conflict in logic built-in se...
Patent number
7,096,397
Issue date
Aug 22, 2006
Intel Corporation
Sandip Kundu
G11 - INFORMATION STORAGE
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Patent Grant
Constrained signature-based test
Patent number
6,510,398
Issue date
Jan 21, 2003
Intel Corporation
Sandip Kundu
G01 - MEASURING TESTING
Patents Applications
last 30 patents
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Patent Application
DEVICE, SYSTEM, AND METHOD FOR OPTIMIZED CONCURRENT ERROR DETECTION
Publication number
20090172529
Publication date
Jul 2, 2009
Intel Corporation
Abhijit Jas
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
Dft technique for avoiding contention/conflict in logic built-in se...
Publication number
20030053358
Publication date
Mar 20, 2003
Intel Corporation
Sandip Kundu
G11 - INFORMATION STORAGE