Rajesh Khurana

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Noida, IN

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Patents Grantslast 30 patents

Information Patent Grant
3D stacked die testing structure
- Patent number 12,055,586
- Issue date Aug 6, 2024
- Cadence Design Systems, Inc.
- Sagar Kumar
- G01 - MEASURING TESTING
Information Patent Grant
IC chip test engine
- Patent number 11,379,644
- Issue date Jul 5, 2022
- Cadence Design Systems, Inc.
- Rajesh Khurana
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compacting test patterns for IJTAG test
- Patent number 10,796,041
- Issue date Oct 6, 2020
- Cadence Design Systems, Inc.
- Rajesh Khurana
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Verification process for IJTAG based test pattern migration
- Patent number 10,528,689
- Issue date Jan 7, 2020
- Cadence Design Systems, Inc.
- Rajesh Khurana
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchical compaction for test pattern power generation
- Patent number 9,170,301
- Issue date Oct 27, 2015
- Cadence Design Systems, Inc.
- Patrick Gallagher
- G01 - MEASURING TESTING
Information Patent Grant
Method and system for analyzing test vectors to determine toggle co...
- Patent number 8,615,692
- Issue date Dec 24, 2013
- Cadence Design Systems, Inc.
- Rajesh Khurana
- G01 - MEASURING TESTING