Rajesh Kumar

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Three-dimensional memory arrays with layer selector transistors
- Patent number 12,114,479
- Issue date Oct 8, 2024
- Intel Corporation
- Wilfred Gomes
- G11 - INFORMATION STORAGE
Information Patent Grant
Hyperchip
- Patent number 12,074,138
- Issue date Aug 27, 2024
- Intel Corporation
- Mark T. Bohr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three-dimensional nanoribbon-based dynamic random-access memory
- Patent number 12,058,849
- Issue date Aug 6, 2024
- Intel Corporation
- Wilfred Gomes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hyperchip
- Patent number 11,984,430
- Issue date May 14, 2024
- Intel Corporation
- Mark T. Bohr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Distributed semiconductor die and package architecture
- Patent number 11,894,359
- Issue date Feb 6, 2024
- Intel Corporation
- Wilfred Gomes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device, system and method for providing inductor structures
- Patent number 11,830,829
- Issue date Nov 28, 2023
- Intel Corporation
- Wilfred Gomes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hyperchip
- Patent number 11,824,041
- Issue date Nov 21, 2023
- Intel Corporation
- Mark T. Bohr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device, method and system for providing a stacked arrangement of in...
- Patent number 11,749,663
- Issue date Sep 5, 2023
- Intel Corporation
- Wilfred Gomes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device, system and method for providing inductor structures
- Patent number 11,387,198
- Issue date Jul 12, 2022
- Intel Corporation
- Wilfred Gomes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device, method and system for providing a stacked arrangement of in...
- Patent number 11,373,987
- Issue date Jun 28, 2022
- Intel Corporation
- Wilfred Gomes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Distribution of tasks among asymmetric processing elements
- Patent number 11,366,511
- Issue date Jun 21, 2022
- Intel Corporation
- Herbert Hum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transistors with back-side contacts to create three dimensional mem...
- Patent number 11,335,686
- Issue date May 17, 2022
- Intel Corporation
- Wilfred Gomes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Distributed semiconductor die and package architecture
- Patent number 11,257,804
- Issue date Feb 22, 2022
- Intel Corporation
- Wilfred Gomes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three-dimensional nanoribbon-based dynamic random-access memory
- Patent number 11,257,822
- Issue date Feb 22, 2022
- Intel Corporation
- Wilfred Gomes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three-dimensional memory arrays with layer selector transistors
- Patent number 11,139,300
- Issue date Oct 5, 2021
- Intel Corporation
- Wilfred Gomes
- G11 - INFORMATION STORAGE
Information Patent Grant
Distribution of tasks among asymmetric processing elements
- Patent number 11,054,890
- Issue date Jul 6, 2021
- Intel Corporation
- Herbert Hum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dense memory arrays utilizing access transistors with back-side con...
- Patent number 11,056,492
- Issue date Jul 6, 2021
- Intel Corporation
- Wilfred Gomes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hyperchip
- Patent number 11,024,601
- Issue date Jun 1, 2021
- Intel Corporation
- Mark T. Bohr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three-dimensional nanoribbon-based logic
- Patent number 11,018,264
- Issue date May 25, 2021
- Intel Corporation
- Wilfred Gomes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Distributed semiconductor die and package architecture
- Patent number 10,685,947
- Issue date Jun 16, 2020
- Intel Corporation
- Wilfred Gomes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Distribution of tasks among asymmetric processing elements
- Patent number 10,437,320
- Issue date Oct 8, 2019
- Intel Corporation
- Herbert Hum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distribution of tasks among asymmetric processing elements
- Patent number 10,409,360
- Issue date Sep 10, 2019
- Intel Corporation
- Herbert Hum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distribution of tasks among asymmetric processing elements
- Patent number 10,386,915
- Issue date Aug 20, 2019
- Intel Corporation
- Herbert Hum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for migrating processes among asymmetrical proc...
- Patent number 9,939,882
- Issue date Apr 10, 2018
- Intel Corporation
- Herbert Hum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distribution of tasks among asymmetric processing elements
- Patent number 9,910,483
- Issue date Mar 6, 2018
- Intel Corporation
- Herbert Hum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distribution of tasks among asymmetric processing elements
- Patent number 9,874,926
- Issue date Jan 23, 2018
- Intel Corporation
- Herbert Hum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distribution of tasks among asymmetric processing elements
- Patent number 9,870,046
- Issue date Jan 16, 2018
- Intel Corporation
- Herbert Hum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distribution of tasks among asymmetric processing elements
- Patent number 9,829,965
- Issue date Nov 28, 2017
- Intel Corporation
- Herbert Hum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distribution of tasks among asymmetric processing elements
- Patent number 9,760,162
- Issue date Sep 12, 2017
- Intel Corporation
- Herbert Hum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distribution of tasks among asymmetric processing elements
- Patent number 9,753,530
- Issue date Sep 5, 2017
- Intel Corporation
- Herbert Hum
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
THREE-DIMENSIONAL MEMORY ARRAYS WITH LAYER SELECTOR TRANSISTORS
- Publication number 20240389300
- Publication date Nov 21, 2024
- Intel Corporation
- Wilfred Gomes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HYPERCHIP
- Publication number 20240243099
- Publication date Jul 18, 2024
- Intel Corporation
- Mark T. BOHR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HYPERCHIP
- Publication number 20240038722
- Publication date Feb 1, 2024
- Intel Corporation
- Mark T. BOHR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HYPERCHIP
- Publication number 20230238357
- Publication date Jul 27, 2023
- Intel Corporation
- Mark T. BOHR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE, SYSTEM AND METHOD FOR PROVIDING INDUCTOR STRUCTURES
- Publication number 20220302051
- Publication date Sep 22, 2022
- Intel Corporation
- Wilfred GOMES
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE, METHOD AND SYSTEM FOR PROVIDING A STACKED ARRANGEMENT OF IN...
- Publication number 20220271022
- Publication date Aug 25, 2022
- Intel Corporation
- Wilfred GOMES
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DISTRIBUTED SEMICONDUCTOR DIE AND PACKAGE ARCHITECTURE
- Publication number 20220139896
- Publication date May 5, 2022
- Intel Corporation
- WILFRED GOMES
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL NANORIBBON-BASED DYNAMIC RANDOM-ACCESS MEMORY
- Publication number 20220068931
- Publication date Mar 3, 2022
- Intel Corporation
- Wilfred Gomes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL MEMORY ARRAYS WITH LAYER SELECTOR TRANSISTORS
- Publication number 20210335791
- Publication date Oct 28, 2021
- Intel Corporation
- Wilfred Gomes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HYPERCHIP
- Publication number 20210225808
- Publication date Jul 22, 2021
- Intel Corporation
- Mark T. BOHR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DENSE MEMORY ARRAYS UTILIZING ACCESS TRANSISTORS WITH BACK-SIDE CON...
- Publication number 20210193666
- Publication date Jun 24, 2021
- Intel Corporation
- Wilfred Gomes
- G11 - INFORMATION STORAGE
Information Patent Application
THREE-DIMENSIONAL NANORIBBON-BASED LOGIC
- Publication number 20210184052
- Publication date Jun 17, 2021
- Intel Corporation
- Wilfred Gomes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL NANORIBBON-BASED DYNAMIC RANDOM-ACCESS MEMORY
- Publication number 20210159229
- Publication date May 27, 2021
- Intel Corporation
- Wilfred Gomes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL MEMORY ARRAYS WITH LAYER SELECTOR TRANSISTORS
- Publication number 20210151438
- Publication date May 20, 2021
- Intel Corporation
- Wilfred Gomes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTORS WITH BACK-SIDE CONTACTS TO CREATE THREE DIMENSIONAL MEM...
- Publication number 20210134802
- Publication date May 6, 2021
- Intel Corporation
- Wilfred Gomes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DISTRIBUTION OF TASKS AMONG ASYMMETRIC PROCESSING ELEMENTS
- Publication number 20210089113
- Publication date Mar 25, 2021
- Intel Corporation
- Herbert Hum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEVICE, METHOD AND SYSTEM FOR PROVIDING A STACKED ARRANGEMENT OF IN...
- Publication number 20210074695
- Publication date Mar 11, 2021
- Intel Corporation
- Wilfred GOMES
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DISTRIBUTED SEMICONDUCTOR DIE AND PACKAGE ARCHITECTURE
- Publication number 20200312833
- Publication date Oct 1, 2020
- Intel Corporation
- WILFRED GOMES
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE, SYSTEM AND METHOD FOR PROVIDING INDUCTOR STRUCTURES
- Publication number 20200258852
- Publication date Aug 13, 2020
- Intel Corporation
- Wilfred GOMES
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ACTIVE SILICON BRIDGE
- Publication number 20200144186
- Publication date May 7, 2020
- Intel Corporation
- Thomas P. THOMAS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HYPERCHIP
- Publication number 20200066679
- Publication date Feb 27, 2020
- Intel Corporation
- Mark T. BOHR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DISTRIBUTED SEMICONDUCTOR DIE AND PACKAGE ARCHITECTURE
- Publication number 20190221556
- Publication date Jul 18, 2019
- WILFRED GOMES
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Distribution of Tasks Among Asymmetric Processing Elements
- Publication number 20170024001
- Publication date Jan 26, 2017
- HERBERT HUM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Distribution of Tasks Among Asymmetric Processing Elements
- Publication number 20160370852
- Publication date Dec 22, 2016
- HERBERT HUM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Distribution of Tasks Among Asymmetric Processing Elements
- Publication number 20160370851
- Publication date Dec 22, 2016
- HERBERT HUM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISTRIBUTION OF TASKS AMONG ASYMMETRIC PROCESSING ELEMENTS
- Publication number 20150012766
- Publication date Jan 8, 2015
- Herbert HUM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISTRIBUTION OF TASKS AMONG ASYMMETRIC PROCESSING ELEMENTS
- Publication number 20150012765
- Publication date Jan 8, 2015
- Herbert HUM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISTRIBUTION OF TASKS AMONG ASYMMETRIC PROCESSING ELEMENTS
- Publication number 20150012731
- Publication date Jan 8, 2015
- Herbert HUM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERCONNECTION OF MULTIPLE CHIPS IN A PACKAGE UTILIZING ON-PACKAGE...
- Publication number 20140201405
- Publication date Jul 17, 2014
- Thomas P. Thomas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISTRIBUTION OF TASKS AMONG ASYMMETRIC PROCESSING ELEMENTS
- Publication number 20140130058
- Publication date May 8, 2014
- Herbert Hum
- G06 - COMPUTING CALCULATING COUNTING

Rajesh Kumar

Person

Patents Grantslast 30 patents

Three-dimensional memory arrays with layer selector transistors

Hyperchip

Three-dimensional nanoribbon-based dynamic random-access memory

Hyperchip

Distributed semiconductor die and package architecture

Device, system and method for providing inductor structures

Hyperchip

Device, method and system for providing a stacked arrangement of in...

Device, system and method for providing inductor structures

Device, method and system for providing a stacked arrangement of in...

Distribution of tasks among asymmetric processing elements

Transistors with back-side contacts to create three dimensional mem...

Distributed semiconductor die and package architecture

Three-dimensional nanoribbon-based dynamic random-access memory

Three-dimensional memory arrays with layer selector transistors

Distribution of tasks among asymmetric processing elements

Dense memory arrays utilizing access transistors with back-side con...

Hyperchip

Three-dimensional nanoribbon-based logic

Distributed semiconductor die and package architecture

Distribution of tasks among asymmetric processing elements

Distribution of tasks among asymmetric processing elements

Distribution of tasks among asymmetric processing elements

Systems and methods for migrating processes among asymmetrical proc...

Distribution of tasks among asymmetric processing elements

Distribution of tasks among asymmetric processing elements

Distribution of tasks among asymmetric processing elements

Distribution of tasks among asymmetric processing elements

Distribution of tasks among asymmetric processing elements

Distribution of tasks among asymmetric processing elements

Patents Applicationslast 30 patents

THREE-DIMENSIONAL MEMORY ARRAYS WITH LAYER SELECTOR TRANSISTORS

HYPERCHIP

HYPERCHIP

HYPERCHIP

DEVICE, SYSTEM AND METHOD FOR PROVIDING INDUCTOR STRUCTURES

DEVICE, METHOD AND SYSTEM FOR PROVIDING A STACKED ARRANGEMENT OF IN...

DISTRIBUTED SEMICONDUCTOR DIE AND PACKAGE ARCHITECTURE

THREE-DIMENSIONAL NANORIBBON-BASED DYNAMIC RANDOM-ACCESS MEMORY

THREE-DIMENSIONAL MEMORY ARRAYS WITH LAYER SELECTOR TRANSISTORS

HYPERCHIP

DENSE MEMORY ARRAYS UTILIZING ACCESS TRANSISTORS WITH BACK-SIDE CON...

THREE-DIMENSIONAL NANORIBBON-BASED LOGIC

THREE-DIMENSIONAL NANORIBBON-BASED DYNAMIC RANDOM-ACCESS MEMORY

THREE-DIMENSIONAL MEMORY ARRAYS WITH LAYER SELECTOR TRANSISTORS

TRANSISTORS WITH BACK-SIDE CONTACTS TO CREATE THREE DIMENSIONAL MEM...

DISTRIBUTION OF TASKS AMONG ASYMMETRIC PROCESSING ELEMENTS

DEVICE, METHOD AND SYSTEM FOR PROVIDING A STACKED ARRANGEMENT OF IN...

DISTRIBUTED SEMICONDUCTOR DIE AND PACKAGE ARCHITECTURE

DEVICE, SYSTEM AND METHOD FOR PROVIDING INDUCTOR STRUCTURES

ACTIVE SILICON BRIDGE

HYPERCHIP

DISTRIBUTED SEMICONDUCTOR DIE AND PACKAGE ARCHITECTURE

Distribution of Tasks Among Asymmetric Processing Elements

Distribution of Tasks Among Asymmetric Processing Elements

Distribution of Tasks Among Asymmetric Processing Elements

DISTRIBUTION OF TASKS AMONG ASYMMETRIC PROCESSING ELEMENTS

DISTRIBUTION OF TASKS AMONG ASYMMETRIC PROCESSING ELEMENTS

DISTRIBUTION OF TASKS AMONG ASYMMETRIC PROCESSING ELEMENTS

INTERCONNECTION OF MULTIPLE CHIPS IN A PACKAGE UTILIZING ON-PACKAGE...

DISTRIBUTION OF TASKS AMONG ASYMMETRIC PROCESSING ELEMENTS