Rajesh Nair

Person

Fremont, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Scaled-out transport as connection proxy for device-to-device commu...
- Patent number 11,637,773
- Issue date Apr 25, 2023
- Fungible, Inc.
- Wael Noureddine
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Efficient arithimetic logic units
- Patent number 9,098,262
- Issue date Aug 4, 2015
- Juniper Networks, Inc.
- Jean-Marc Frailong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Emulation of multiple instruction sets
- Patent number 9,026,424
- Issue date May 5, 2015
- Juniper Networks, Inc.
- Jeffrey G. Libby
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient arithmetic logic units
- Patent number 8,880,856
- Issue date Nov 4, 2014
- Juniper Networks, Inc.
- Jean-Marc Frailong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for efficient packet replication
- Patent number 8,520,675
- Issue date Aug 27, 2013
- Juniper Networks, Inc.
- Jean-Marc Frailong
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Hardware support for instruction set emulation
- Patent number 8,069,023
- Issue date Nov 29, 2011
- Juniper Networks, Inc.
- Jean-Marc Frailong
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Symbol parsing architecture
- Patent number 7,478,223
- Issue date Jan 13, 2009
- Gigafin Networks, Inc.
- Somsubhra Sikdar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parser table/production rule table configuration using CAM and SRAM
- Patent number 7,415,596
- Issue date Aug 19, 2008
- Gigafin Networks, Inc.
- Somsubhra Sikdar
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SCALED-OUT TRANSPORT AS CONNECTION PROXY FOR DEVICE-TO-DEVICE COMMU...
- Publication number 20230224247
- Publication date Jul 13, 2023
- Fungible, Inc.
- Wael Noureddine
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SCALED-OUT TRANSPORT AS CONNECTION PROXY FOR DEVICE-TO-DEVICE COMMU...
- Publication number 20210250285
- Publication date Aug 12, 2021
- Fungible, Inc.
- Wael Noureddine
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
EFFICIENT ARTHIMETIC LOGIC UNITS
- Publication number 20150058599
- Publication date Feb 26, 2015
- Juniper Networks, Inc.
- Jean-Marc FRAILONG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Debug non-terminal symbol for parser error handling
- Publication number 20070043871
- Publication date Feb 22, 2007
- Mistletoe Technologies, Inc.
- Jonathan Sweedler
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Packet output buffer for semantic processor
- Publication number 20070019661
- Publication date Jan 25, 2007
- Mistletoe Technologies, Inc.
- Kevin Jerome Rowett
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory DMA interface with checksum
- Publication number 20070022225
- Publication date Jan 25, 2007
- Mistletoe Technologies, Inc.
- Rajesh Nair
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Efficient hardware allocation of processes to processors
- Publication number 20070016906
- Publication date Jan 18, 2007
- Mistletoe Technologies, Inc.
- Richard D. Trauben
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Recirculation buffer for semantic processor
- Publication number 20060174058
- Publication date Aug 3, 2006
- Somsubhra Sikdar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Symbol parsing architecture
- Publication number 20060168309
- Publication date Jul 27, 2006
- Mistletoe Technologies, Inc.
- Somsubhra Sikdar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Parser table/production rule table configuration using CAM and SRAM
- Publication number 20060010193
- Publication date Jan 12, 2006
- Mistletoe Technologies, Inc.
- Somsubhra Sikdar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Port input buffer architecture
- Publication number 20050281281
- Publication date Dec 22, 2005
- Rajesh Nair
- G06 - COMPUTING CALCULATING COUNTING

Rajesh Nair

Person

Patents Grantslast 30 patents

Scaled-out transport as connection proxy for device-to-device commu...

Efficient arithimetic logic units

Emulation of multiple instruction sets

Efficient arithmetic logic units

System and method for efficient packet replication

Hardware support for instruction set emulation

Symbol parsing architecture

Parser table/production rule table configuration using CAM and SRAM

Patents Applicationslast 30 patents

SCALED-OUT TRANSPORT AS CONNECTION PROXY FOR DEVICE-TO-DEVICE COMMU...

SCALED-OUT TRANSPORT AS CONNECTION PROXY FOR DEVICE-TO-DEVICE COMMU...

EFFICIENT ARTHIMETIC LOGIC UNITS

Debug non-terminal symbol for parser error handling

Packet output buffer for semantic processor

Memory DMA interface with checksum

Efficient hardware allocation of processes to processors

Recirculation buffer for semantic processor

Symbol parsing architecture

Parser table/production rule table configuration using CAM and SRAM

Port input buffer architecture