Rajesh Surapaneni

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Portland, OR, US

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Patents Applicationslast 30 patents

Information Patent Application
PACKAGING ARCHITECTURE FOR WAFER-SCALE KNOWN-GOOD-DIE HYBRID BONDING
- Publication number 20250006678
- Publication date Jan 2, 2025
- Intel Corporation
- Omkar G. Karhade
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING DIE STRUCTURES WITH SCALLOPED SIDEWALLS AND STRU...
- Publication number 20240332353
- Publication date Oct 3, 2024
- Intel Corporation
- Xavier F. Brun
- H01 - BASIC ELECTRIC ELEMENTS