Rajiv Kumar Sisodia

Person

Bangalore, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Backside power supply techniques
- Patent number 12,218,664
- Issue date Feb 4, 2025
- ARM Limited
- Sriram Thyagarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bitcell architecture using buried metal
- Patent number 11,901,290
- Issue date Feb 13, 2024
- ARM Limited
- Rajiv Kumar Sisodia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wordline modulation techniques
- Patent number 11,900,995
- Issue date Feb 13, 2024
- ARM Limited
- Rajiv Kumar Sisodia
- G11 - INFORMATION STORAGE
Information Patent Grant
Wordline coupling techniques
- Patent number 11,830,542
- Issue date Nov 28, 2023
- ARM Limited
- Rajiv Kumar Sisodia
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory architecture with DC biasing
- Patent number 11,676,656
- Issue date Jun 13, 2023
- ARM Limited
- Andy Wangkun Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Flexible sizing and routing architecture
- Patent number 11,631,439
- Issue date Apr 18, 2023
- ARM Limited
- Sriram Thyagarajan
- G11 - INFORMATION STORAGE
Information Patent Grant
Wordline driver architecture
- Patent number 11,514,979
- Issue date Nov 29, 2022
- ARM Limited
- Andy Wangkun Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Wordline coupling techniques
- Patent number 11,430,506
- Issue date Aug 30, 2022
- ARM Limited
- Rajiv Kumar Sisodia
- G11 - INFORMATION STORAGE
Information Patent Grant
Power-gating techniques with buried metal
- Patent number 11,322,197
- Issue date May 3, 2022
- ARM Limited
- Rajiv Kumar Sisodia
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques for powering memory
- Patent number 11,315,628
- Issue date Apr 26, 2022
- ARM Limited
- Rajiv Kumar Sisodia
- G11 - INFORMATION STORAGE
Information Patent Grant
Bitline precharging techniques
- Patent number 11,100,965
- Issue date Aug 24, 2021
- ARM Limited
- Rajiv Kumar Sisodia
- G11 - INFORMATION STORAGE
Information Patent Grant
Tri-state buffering techniques
- Patent number 11,074,945
- Issue date Jul 27, 2021
- ARM Limited
- Rajiv Kumar Sisodia
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory with a controllable I/O functional unit
- Patent number 10,861,575
- Issue date Dec 8, 2020
- ARM Limited
- Rajiv Kumar Sisodia
- G11 - INFORMATION STORAGE
Information Patent Grant
Providing a discharge boundary using bitline discharge control circ...
- Patent number 10,734,065
- Issue date Aug 4, 2020
- ARM Limited
- Rajiv Kumar Sisodia
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory with a controllable I/O functional unit
- Patent number 10,460,822
- Issue date Oct 29, 2019
- ARM Limited
- Rajiv Kumar Sisodia
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
FLEXIBLE SIZING AND ROUTING ARCHITECTURE
- Publication number 20230136348
- Publication date May 4, 2023
- ARM Limited
- Sriram Thyagarajan
- G11 - INFORMATION STORAGE
Information Patent Application
Wordline Coupling Techniques
- Publication number 20220415385
- Publication date Dec 29, 2022
- ARM Limited
- Rajiv Kumar Sisodia
- G11 - INFORMATION STORAGE
Information Patent Application
Wordline Driver Architecture
- Publication number 20220319585
- Publication date Oct 6, 2022
- ARM Limited
- Andy Wangkun Chen
- G11 - INFORMATION STORAGE
Information Patent Application
Wordline Modulation Techniques
- Publication number 20220319586
- Publication date Oct 6, 2022
- ARM Limited
- Rajiv Kumar Sisodia
- G11 - INFORMATION STORAGE
Information Patent Application
Memory Architecture with DC Biasing
- Publication number 20220254411
- Publication date Aug 11, 2022
- ARM Limited
- Andy Wangkun Chen
- G11 - INFORMATION STORAGE
Information Patent Application
Bitcell Architecture Using Buried Metal
- Publication number 20220223514
- Publication date Jul 14, 2022
- ARM Limited
- Rajiv Kumar Sisodia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Techniques For Powering Memory
- Publication number 20220122654
- Publication date Apr 21, 2022
- ARM Limited
- Rajiv Kumar Sisodia
- G11 - INFORMATION STORAGE
Information Patent Application
Backside Power Supply Techniques
- Publication number 20220123751
- Publication date Apr 21, 2022
- ARM Limited
- Sriram Thyagarajan
- G11 - INFORMATION STORAGE
Information Patent Application
Power-Gating Techniques with Buried Metal
- Publication number 20220122656
- Publication date Apr 21, 2022
- ARM Limited
- Rajiv Kumar Sisodia
- G11 - INFORMATION STORAGE
Information Patent Application
Wordline Coupling Techniques
- Publication number 20210249070
- Publication date Aug 12, 2021
- ARM Limited
- Rajiv Kumar Sisodia
- G11 - INFORMATION STORAGE
Information Patent Application
Memory with a Controllable I/O Functional Unit
- Publication number 20200066365
- Publication date Feb 27, 2020
- ARM Limited
- Rajiv Kumar Sisodia
- G11 - INFORMATION STORAGE
Information Patent Application
Bitline Discharge Control Circuitry
- Publication number 20190066770
- Publication date Feb 28, 2019
- ARM Limited
- Rajiv Kumar Sisodia
- G11 - INFORMATION STORAGE
Information Patent Application
Memory with a Controllable I/O Functional Unit
- Publication number 20190066814
- Publication date Feb 28, 2019
- ARM Limited
- Rajiv Kumar Sisodia
- G11 - INFORMATION STORAGE

Rajiv Kumar Sisodia

Person

Patents Grantslast 30 patents

Backside power supply techniques

Bitcell architecture using buried metal

Wordline modulation techniques

Wordline coupling techniques

Memory architecture with DC biasing

Flexible sizing and routing architecture

Wordline driver architecture

Wordline coupling techniques

Power-gating techniques with buried metal

Techniques for powering memory

Bitline precharging techniques

Tri-state buffering techniques

Memory with a controllable I/O functional unit

Providing a discharge boundary using bitline discharge control circ...

Memory with a controllable I/O functional unit

Patents Applicationslast 30 patents

FLEXIBLE SIZING AND ROUTING ARCHITECTURE

Wordline Coupling Techniques

Wordline Driver Architecture

Wordline Modulation Techniques

Memory Architecture with DC Biasing

Bitcell Architecture Using Buried Metal

Techniques For Powering Memory

Backside Power Supply Techniques

Power-Gating Techniques with Buried Metal

Wordline Coupling Techniques

Memory with a Controllable I/O Functional Unit

Bitline Discharge Control Circuitry

Memory with a Controllable I/O Functional Unit