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Rajvinder S. Klair
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San Jose, CA, US
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Patents Grants
last 30 patents
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Patent Grant
Hierarchical access simulation for signaling with more than two sta...
Patent number
11,543,452
Issue date
Jan 3, 2023
Xilinx, Inc.
Saikat Bandyopadhyay
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Protection of high-level language simulation models
Patent number
11,281,834
Issue date
Mar 22, 2022
Xilinx, Inc.
Rajvinder S. Klair
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Linking of simulators into a circuit design tool
Patent number
9,646,118
Issue date
May 9, 2017
Xilinx, Inc.
Rajvinder S. Klair
G06 - COMPUTING CALCULATING COUNTING
Patents Applications
last 30 patents
Information
Patent Application
ADAPTABLE FRAMEWORK FOR CIRCUIT DESIGN SIMULATION VERIFICATION
Publication number
20240232482
Publication date
Jul 11, 2024
Xilinx, Inc.
Saikat Bandyopadhyay
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
ADAPTABLE FRAMEWORK FOR CIRCUIT DESIGN SIMULATION VERIFICATION
Publication number
20240135074
Publication date
Apr 25, 2024
Xilinx, Inc.
Saikat Bandyopadhyay
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
TESTBENCH FOR SUB-DESIGN VERIFICATION
Publication number
20230252212
Publication date
Aug 10, 2023
Xilinx, Inc.
Rajvinder S. Klair
G06 - COMPUTING CALCULATING COUNTING