Ralf Ludewig

Person

Schoenaich, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Reduced simulation verification complexity of cache purge
- Patent number 11,860,789
- Issue date Jan 2, 2024
- International Business Machines Corporation
- Yvo Thomas Bernard Mulder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synchronous clock stop in a multi nodal computer system
- Patent number 8,868,960
- Issue date Oct 21, 2014
- International Business Machines Corporation
- Tobias Bergmann
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Integrated circuit arrangement for test inputs
- Patent number 8,479,070
- Issue date Jul 2, 2013
- International Business Machines Corporation
- Ulrich Baur
- G01 - MEASURING TESTING
Information Patent Grant
Method for switching between two redundant oscillator signals withi...
- Patent number 8,055,931
- Issue date Nov 8, 2011
- International Business Machines Corporation
- Ralf Ludewig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for automatic scan completion in the event of...
- Patent number 7,966,536
- Issue date Jun 21, 2011
- International Business Machines Corporation
- Ralf Ludewig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for performing a serial communication between a central cont...
- Patent number 7,788,432
- Issue date Aug 31, 2010
- International Business Machines Corporation
- Ralf Ludewig
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
REDUCED SIMULATION VERIFICATION COMPLEXITY OF CACHE PURGE
- Publication number 20230297509
- Publication date Sep 21, 2023
- International Business Machines Corporation
- Yvo Thomas Bernard Mulder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LARGE SCALE FORMAL ANALYSIS BY STRUCTURAL PREPROCESSING
- Publication number 20120151423
- Publication date Jun 14, 2012
- International Business Machines Corporation
- Jason R. Baumgartner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYNCHRONOUS CLOCK STOP IN A MULTI NODAL COMPUTER SYSTEM
- Publication number 20120005516
- Publication date Jan 5, 2012
- International Business Machines Corporation
- Tobias BERGMANN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrated Circuit Arrangement For Test Inputs
- Publication number 20110320898
- Publication date Dec 29, 2011
- International Business Machines Corporation
- Ulrich Baur
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND APPARATUS FOR AUTOMATIC SCAN COMPLETION IN THE EVENT OF...
- Publication number 20090259899
- Publication date Oct 15, 2009
- Ralf Ludewig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System for performing a serial communication between a central cont...
- Publication number 20090113094
- Publication date Apr 30, 2009
- International Business Machines Corporation
- Ralf Ludewig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for switching between two redundant oscillator signals withi...
- Publication number 20090100283
- Publication date Apr 16, 2009
- International Business Machines Corporation
- Ralf Ludewig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method to Resolve Deadlock in a Bus Architecture Comprising Two Sin...
- Publication number 20080276022
- Publication date Nov 6, 2008
- International Business Machines Corporation
- Thuyen Le
- G06 - COMPUTING CALCULATING COUNTING

Ralf Ludewig

Person

Patents Grantslast 30 patents

Reduced simulation verification complexity of cache purge

Synchronous clock stop in a multi nodal computer system

Integrated circuit arrangement for test inputs

Method for switching between two redundant oscillator signals withi...

Method and apparatus for automatic scan completion in the event of...

System for performing a serial communication between a central cont...

Patents Applicationslast 30 patents

REDUCED SIMULATION VERIFICATION COMPLEXITY OF CACHE PURGE

LARGE SCALE FORMAL ANALYSIS BY STRUCTURAL PREPROCESSING

SYNCHRONOUS CLOCK STOP IN A MULTI NODAL COMPUTER SYSTEM

Integrated Circuit Arrangement For Test Inputs

METHOD AND APPARATUS FOR AUTOMATIC SCAN COMPLETION IN THE EVENT OF...

System for performing a serial communication between a central cont...

Method for switching between two redundant oscillator signals withi...

Method to Resolve Deadlock in a Bus Architecture Comprising Two Sin...