Ralph D. Wittig

Person

Menlo Park, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Data processing engine arrangement in a device
- Patent number 11,972,132
- Issue date Apr 30, 2024
- Xilinx, Inc.
- Juan J. Noguera Serra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Control and reconfiguration of data flow graphs on heterogeneous co...
- Patent number 11,687,327
- Issue date Jun 27, 2023
- Xilinx, Inc.
- Chia-Jui Hsu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data processing engine arrangement in a device
- Patent number 11,573,726
- Issue date Feb 7, 2023
- Xilinx, Inc.
- Juan J. Noguera Serra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Control and reconfiguration of data flow graphs on heterogeneous co...
- Patent number 11,281,440
- Issue date Mar 22, 2022
- Xilinx, Inc.
- Chia-Jui Hsu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dataflow graph programming environment for a heterogenous processin...
- Patent number 11,204,745
- Issue date Dec 21, 2021
- Xilinx, Inc.
- Shail Aditya Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Streaming interconnect architecture for data processing engine array
- Patent number 10,990,552
- Issue date Apr 27, 2021
- Xilinx, Inc.
- Goran Hk Bilski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data processing engine arrangement in a device
- Patent number 10,866,753
- Issue date Dec 15, 2020
- Xilinx, Inc.
- Juan J. Noguera Serra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compilation flow for a heterogeneous multi-core architecture
- Patent number 10,860,766
- Issue date Dec 8, 2020
- Xilinx, Inc.
- Mukund Sivaraman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamically structured single instruction, multiple data (SIMD) ins...
- Patent number 10,824,434
- Issue date Nov 3, 2020
- Xilinx, Inc.
- Sean Settle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Control and reconfiguration of data flow graphs on heterogeneous co...
- Patent number 10,802,807
- Issue date Oct 13, 2020
- Xilinx, Inc.
- Chia-Jui Hsu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device with data processing engine array
- Patent number 10,747,690
- Issue date Aug 18, 2020
- Xilinx, Inc.
- Goran H K Bilski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Heterogeneous multiprocessor platform targeting programmable integr...
- Patent number 9,846,660
- Issue date Dec 19, 2017
- Xilinx, Inc.
- Henry E. Styles
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Heterogeneous multiprocessor program compilation targeting programm...
- Patent number 9,218,443
- Issue date Dec 22, 2015
- Xilinx, Inc.
- Henry E. Styles
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transaction-level lockstep
- Patent number 8,479,042
- Issue date Jul 2, 2013
- Xilinx, Inc.
- Philip B. James-Roxby
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coprocessor interface architecture and methods of operating the same
- Patent number 8,447,957
- Issue date May 21, 2013
- Xilinx, Inc.
- Jorge Ernesto Carrillo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and systems with transaction-level lockstep
- Patent number 8,443,230
- Issue date May 14, 2013
- Xilinx, Inc.
- Philip B. James-Roxby
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Segmentation and reassembly of a data value communicated via interr...
- Patent number 8,352,659
- Issue date Jan 8, 2013
- Xilinx, Inc.
- Henry E. Styles
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Providing multiple selectable configuration sources for programmabl...
- Patent number 8,296,557
- Issue date Oct 23, 2012
- Xilinx, Inc.
- Richard S. Ballantyne
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method for open drain/open collector structures in an in...
- Patent number 7,948,269
- Issue date May 24, 2011
- Xilinx, Inc.
- Richard S. Ballantyne
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Generic buffer circuits and methods for out of band signaling
- Patent number 7,786,762
- Issue date Aug 31, 2010
- Xilinx, Inc.
- Richard S. Ballantyne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Event-driven simulation of IP using third party event-driven simula...
- Patent number 7,721,090
- Issue date May 18, 2010
- Xilinx, Inc.
- Kumar Deepak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for fast linked processor in a system on a chip (...
- Patent number 7,340,585
- Issue date Mar 4, 2008
- Xilinx, Inc.
- Satish R. Ganesan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for designing a multiprocessor
- Patent number 7,310,594
- Issue date Dec 18, 2007
- Xilinx, Inc.
- Satish R. Ganesan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable logic element with expander structures
- Patent number 7,248,073
- Issue date Jul 24, 2007
- Xilinx, Inc.
- Bernard J. New
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for providing self-implementing hardware-softw...
- Patent number 7,243,330
- Issue date Jul 10, 2007
- Xilinx, Inc.
- Satish R. Ganesan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Structures and methods providing columns of tightly coupled process...
- Patent number 7,181,718
- Issue date Feb 20, 2007
- Xilinx, Inc.
- Goran Bilski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable logic element with expander structures
- Patent number 7,145,360
- Issue date Dec 5, 2006
- Xilinx, Inc.
- Bernard J. New
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Softpal implementation and mapping technology for FPGAs with dedica...
- Patent number 7,111,273
- Issue date Sep 19, 2006
- Xilinx, Inc.
- Satish R. Ganesan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Structures and methods providing columns of tightly coupled process...
- Patent number 6,946,874
- Issue date Sep 20, 2005
- Xilinx, Inc.
- Goran Bilski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable logic element with expander structures
- Patent number 6,847,229
- Issue date Jan 25, 2005
- Xilinx, Inc.
- Bernard J. New
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
OPTIMIZING LOW PRECISION AND SPARSITY INFERENCE WITHOUT RETRAINING
- Publication number 20240211762
- Publication date Jun 27, 2024
- ADVANCED MICRO DEVICES, INC.
- Adam H. Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTROL AND RECONFIGURATION OF DATA FLOW GRAPHS ON HETEROGENEOUS CO...
- Publication number 20220206766
- Publication date Jun 30, 2022
- Xilinx, Inc.
- Chia-Jui HSU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATAFLOW GRAPH PROGRAMMING ENVIRONMENT FOR A HETEROGENOUS PROCESSIN...
- Publication number 20220058005
- Publication date Feb 24, 2022
- Xilinx, Inc.
- Shail Aditya GUPTA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATAFLOW GRAPH PROGRAMMING ENVIRONMENT FOR A HETEROGENOUS PROCESSIN...
- Publication number 20200371761
- Publication date Nov 26, 2020
- Xilinx, Inc.
- Shail Aditya Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPILATION FLOW FOR A HETEROGENEOUS MULTI-CORE ARCHITECTURE
- Publication number 20200372200
- Publication date Nov 26, 2020
- Xilinx, Inc.
- Mukund Sivaraman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA PROCESSING ENGINE ARRANGEMENT IN A DEVICE
- Publication number 20190303033
- Publication date Oct 3, 2019
- Xilinx, Inc.
- Juan J. Noguera Serra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEVICE WITH DATA PROCESSING ENGINE ARRAY
- Publication number 20190303311
- Publication date Oct 3, 2019
- Xilinx, Inc.
- Goran HK Bilski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HETEROGENEOUS MULTIPROCESSOR PLATFORM TARGETING PROGRAMMABLE INTEGR...
- Publication number 20160132441
- Publication date May 12, 2016
- Xilinx, Inc.
- Henry E. Styles
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GENERIC BUFFER CIRCUITS AND METHODS FOR OUT OF BAND SIGNALING
- Publication number 20100183081
- Publication date Jul 22, 2010
- Xilinx, Inc.
- Richard S. Ballantyne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Configurable logic element with expander structures
- Publication number 20070035328
- Publication date Feb 15, 2007
- Xilinx, Inc.
- Bernard J. New
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Configurable logic element with expander structures
- Publication number 20050062498
- Publication date Mar 24, 2005
- Xilinx, Inc.
- Bernard J. New
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Configurable logic element with expander structures
- Publication number 20040032283
- Publication date Feb 19, 2004
- Xilinx, Inc.
- Bernard J. New
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Configurable logic element with expander structures
- Publication number 20020125910
- Publication date Sep 12, 2002
- Xilinx, Inc.
- Bernard J. New
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Configurable logic block for PLD with logic gate for combining outp...
- Publication number 20020079921
- Publication date Jun 27, 2002
- Xilinx, Inc.
- Alireza S. Kaviani
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Configurable logic element with expander structures
- Publication number 20010045844
- Publication date Nov 29, 2001
- Xilinx, Inc.
- Bernard J. New
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Logic/memory circuit having a plurality of operating modes
- Publication number 20010043082
- Publication date Nov 22, 2001
- Xilink, Inc.
- Ralph D. Wittig
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Methods and media for utilizing symbolic expressions in circuit mod...
- Publication number 20010001881
- Publication date May 24, 2001
- Sundararajarao Mohan
- G06 - COMPUTING CALCULATING COUNTING

Ralph D. Wittig

Person

Patents Grantslast 30 patents

Data processing engine arrangement in a device

Control and reconfiguration of data flow graphs on heterogeneous co...

Data processing engine arrangement in a device

Control and reconfiguration of data flow graphs on heterogeneous co...

Dataflow graph programming environment for a heterogenous processin...

Streaming interconnect architecture for data processing engine array

Data processing engine arrangement in a device

Compilation flow for a heterogeneous multi-core architecture

Dynamically structured single instruction, multiple data (SIMD) ins...

Control and reconfiguration of data flow graphs on heterogeneous co...

Device with data processing engine array

Heterogeneous multiprocessor platform targeting programmable integr...

Heterogeneous multiprocessor program compilation targeting programm...

Transaction-level lockstep

Coprocessor interface architecture and methods of operating the same

Methods and systems with transaction-level lockstep

Segmentation and reassembly of a data value communicated via interr...

Providing multiple selectable configuration sources for programmabl...

System and method for open drain/open collector structures in an in...

Generic buffer circuits and methods for out of band signaling

Event-driven simulation of IP using third party event-driven simula...

Method and system for fast linked processor in a system on a chip (...

Method and system for designing a multiprocessor

Configurable logic element with expander structures

Method and apparatus for providing self-implementing hardware-softw...

Structures and methods providing columns of tightly coupled process...

Configurable logic element with expander structures

Softpal implementation and mapping technology for FPGAs with dedica...

Structures and methods providing columns of tightly coupled process...

Configurable logic element with expander structures

Patents Applicationslast 30 patents

OPTIMIZING LOW PRECISION AND SPARSITY INFERENCE WITHOUT RETRAINING

CONTROL AND RECONFIGURATION OF DATA FLOW GRAPHS ON HETEROGENEOUS CO...

DATAFLOW GRAPH PROGRAMMING ENVIRONMENT FOR A HETEROGENOUS PROCESSIN...

DATAFLOW GRAPH PROGRAMMING ENVIRONMENT FOR A HETEROGENOUS PROCESSIN...

COMPILATION FLOW FOR A HETEROGENEOUS MULTI-CORE ARCHITECTURE

DATA PROCESSING ENGINE ARRANGEMENT IN A DEVICE

DEVICE WITH DATA PROCESSING ENGINE ARRAY

HETEROGENEOUS MULTIPROCESSOR PLATFORM TARGETING PROGRAMMABLE INTEGR...

GENERIC BUFFER CIRCUITS AND METHODS FOR OUT OF BAND SIGNALING

Configurable logic element with expander structures

Configurable logic element with expander structures

Configurable logic element with expander structures

Configurable logic element with expander structures

Configurable logic block for PLD with logic gate for combining outp...

Configurable logic element with expander structures

Logic/memory circuit having a plurality of operating modes

Methods and media for utilizing symbolic expressions in circuit mod...