Ramakrishnan Venkatasubramanian

Person

Plano, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Non-volatile memory compression for memory repair
- Patent number 12,259,789
- Issue date Mar 25, 2025
- Texas Instruments Incorporated
- Devanathan Varadarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Zero latency prefetching in caches
- Patent number 12,197,334
- Issue date Jan 14, 2025
- Texas Instruments Incorporated
- Oluleye Olorode
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Servicing CPU demand requests with inflight prefetches
- Patent number 12,124,374
- Issue date Oct 22, 2024
- Texas Instruments Incorporated
- Oluleye Olorode
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Highly integrated scalable, flexible DSP megamodule architecture
- Patent number 12,072,812
- Issue date Aug 27, 2024
- Texas Instruments Incorporated
- Timothy D. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Electrical and logic isolation for systems on a chip
- Patent number 11,774,487
- Issue date Oct 3, 2023
- Texas Instruments Incorporated
- Jose Luis Flores
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit with high-speed clock bypass before reset
- Patent number 11,770,124
- Issue date Sep 26, 2023
- Texas Instruments Incorporated
- Jose Luis Flores
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non-volatile memory compression for memory repair
- Patent number 11,748,202
- Issue date Sep 5, 2023
- Texas Instruments Incorporated
- Devanathan Varadarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Lookahead priority collection to support priority elevation
- Patent number 11,537,532
- Issue date Dec 27, 2022
- Texas Instmments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Servicing CPU demand requests with inflight prefetches
- Patent number 11,500,777
- Issue date Nov 15, 2022
- Texas Instruments Incorporated
- Oluleye Olorode
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Zero latency prefetching in caches
- Patent number 11,474,944
- Issue date Oct 18, 2022
- Texas Instruments Incorporated
- Oluleye Olorode
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non-volatile memory compression for memory repair
- Patent number 11,436,090
- Issue date Sep 6, 2022
- Texas Instmments Incorporated
- Devanathan Varadarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit with high-speed clock bypass before reset
- Patent number 11,196,424
- Issue date Dec 7, 2021
- Texas Instruments Incorporated
- Jose Luis Flores
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Highly integrated scalable, flexible DSP megamodule architecture
- Patent number 11,036,648
- Issue date Jun 15, 2021
- Texas Instruments Incorporated
- Timothy D. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Zero latency prefetching in caches
- Patent number 10,929,296
- Issue date Feb 23, 2021
- Texas Instruments Incorporated
- Oluleye Olorode
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Lookahead priority collection to support priority elevation
- Patent number 10,713,180
- Issue date Jul 14, 2020
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Servicing CPU demand requests with inflight prefetches
- Patent number 10,558,578
- Issue date Feb 11, 2020
- Texas Instruments Incorporated
- Oluleye Olorode
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Servicing CPU demand requests with inflight prefetchs
- Patent number 10,210,090
- Issue date Feb 19, 2019
- Texas Instruments Incorporated
- Oluleye Olorode
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Highly integrated scalable, flexible DSP megamodule architecture
- Patent number 10,162,641
- Issue date Dec 25, 2018
- Texas Instruments Incorporated
- Timothy D. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power switch with source-bias mode for on-chip powerdomain supply d...
- Patent number 9,798,344
- Issue date Oct 24, 2017
- Texas Instruments Incorporated
- Ramakrishnan Venkatasubramanian
- G05 - CONTROLLING REGULATING
Information Patent Grant
Using L1 cache as re-order buffer
- Patent number 9,652,392
- Issue date May 16, 2017
- Texas Instruments Incorporated
- Ramakrishnan Venkatasubramanian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hiding page translation miss latency in program memory controller b...
- Patent number 9,652,402
- Issue date May 16, 2017
- Texas Instruments Incorporated
- Ramakrishnan Venkatasubramanian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-chip power-domain supply drooping for low voltage idle/standby m...
- Patent number 9,618,956
- Issue date Apr 11, 2017
- Texas Instruments Incorporated
- Michael Gill
- G05 - CONTROLLING REGULATING
Information Patent Grant
Highly integrated scalable, flexible DSP megamodule architecture
- Patent number 9,606,803
- Issue date Mar 28, 2017
- Texas Instruments Incorporated
- Timothy D. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Protection of memories, datapath and pipeline registers, and other...
- Patent number 9,557,936
- Issue date Jan 31, 2017
- Texas Instruments Incorporated
- Timothy D. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Local page translation and permissions storage for the page window...
- Patent number 9,514,058
- Issue date Dec 6, 2016
- Texas Instruments Incorporated
- Oluleye Olorode
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hiding page translation miss latency in program memory controller b...
- Patent number 9,514,059
- Issue date Dec 6, 2016
- Texas Instruments Incorporated
- Ramakrishnan Venkatasubramanian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using L1 cache as re-order buffer
- Patent number 9,471,320
- Issue date Oct 18, 2016
- Texas Instruments Incorporated
- Ramakrishnan Venkatasubramanian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power switch with source-bias mode for on-chip powerdomain supply d...
- Patent number 9,417,648
- Issue date Aug 16, 2016
- Texas Instruments Incorporated
- Ramakrishnan Venkatasubramanian
- G05 - CONTROLLING REGULATING
Information Patent Grant
Reducing current leakage in L1 program memory
- Patent number 8,977,878
- Issue date Mar 10, 2015
- Texas Instruments Incorporated
- Ramakrishnan Venkatasubramanian
- G11 - INFORMATION STORAGE
Information Patent Grant
Asynchronous clock dividers to reduce on-chip variations of clock t...
- Patent number 8,970,267
- Issue date Mar 3, 2015
- Texas Instruments Incorporated
- Raguram Damodaran
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
NON-VOLATILE MEMORY COMPRESSION FOR MEMORY REPAIR
- Publication number 20250225034
- Publication date Jul 10, 2025
- TEXAS INSTRUMENTS INCORPORATED
- DEVANATHAN VARADARAJAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ZERO LATENCY PREFETCHING IN CACHES
- Publication number 20250103503
- Publication date Mar 27, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Oluleye Olorode
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SERVICING CPU DEMAND REQUESTS WITH INFLIGHT PREFETCHES
- Publication number 20240419602
- Publication date Dec 19, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Oluleye Olorode
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR ARCHITECTURE WITH MEMORY ACCESS CIRCUIT
- Publication number 20240411703
- Publication date Dec 12, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Timothy D. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ELECTRICAL AND LOGIC ISOLATION FOR SYSTEMS ON A CHIP
- Publication number 20240027515
- Publication date Jan 25, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Jose Luis Flores
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NON-VOLATILE MEMORY COMPRESSION FOR MEMORY REPAIR
- Publication number 20230409435
- Publication date Dec 21, 2023
- TEXAS INSTRUMENTS INCORPORATED
- DEVANATHAN VARADARAJAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOOKAHEAD PRIORITY COLLECTION TO SUPPORT PRIORITY ELEVATION
- Publication number 20230244611
- Publication date Aug 3, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SERVICING CPU DEMAND REQUESTS WITH INFLIGHT PREFETCHES
- Publication number 20230078414
- Publication date Mar 16, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Oluleye Olorode
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ZERO LATENCY PREFETCHING IN CACHES
- Publication number 20230004498
- Publication date Jan 5, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Oluleye Olorode
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NON-VOLATILE MEMORY COMPRESSION FOR MEMORY REPAIR
- Publication number 20220413966
- Publication date Dec 29, 2022
- TEXAS INSTRUMENTS INCORPORATED
- DEVANATHAN VARADARAJAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NON-VOLATILE MEMORY COMPRESSION FOR MEMORY REPAIR
- Publication number 20220197750
- Publication date Jun 23, 2022
- TEXAS INSTRUMENTS INCORPORATED
- DEVANATHAN VARADARAJAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT WITH HIGH-SPEED CLOCK BYPASS BEFORE RESET
- Publication number 20220103179
- Publication date Mar 31, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Jose Luis FLORES
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGHLY INTEGRATED SCALABLE, FLEXIBLE DSP MEGAMODULE ARCHITECTURE
- Publication number 20210240634
- Publication date Aug 5, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Timothy D. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Electrical and Logic Isolation for Systems on a Chip
- Publication number 20210208189
- Publication date Jul 8, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Jose Luis Flores
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT WITH HIGH-SPEED CLOCK BYPASS BEFORE RESET
- Publication number 20210211132
- Publication date Jul 8, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Jose Luis FLORES
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ZERO LATENCY PREFETCHING IN CACHES
- Publication number 20210141732
- Publication date May 13, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Oluleye Olorode
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOOKAHEAD PRIORITY COLLECTION TO SUPPORT PRIORITY ELEVATION
- Publication number 20200401532
- Publication date Dec 24, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SERVICING CPU DEMAND REQUESTS WITH INFLIGHT PREFETCHES
- Publication number 20200167288
- Publication date May 28, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Oluleye Olorode
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SERVICING CPU DEMAND REQUESTS WITH INFLIGHT PREFETCHES
- Publication number 20190179759
- Publication date Jun 13, 2019
- TEXAS INSTRUMENTS INCORPORATED
- Oluleye Olorode
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGHLY INTEGRATED SCALABLE, FLEXIBLE DSP MEGAMODULE ARCHITECTURE
- Publication number 20190146790
- Publication date May 16, 2019
- TEXAS INSTRUMENTS INCORPORATED
- Timothy D. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ZERO LATENCY PREFETCHING IN CACHES
- Publication number 20190114263
- Publication date Apr 18, 2019
- TEXAS INSTRUMENTS INCORPORATED
- Oluleye Olorode
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Lookahead Priority Collection to Support Priority Elevation
- Publication number 20190004967
- Publication date Jan 3, 2019
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok Chachad
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
HIGHLY INTEGRATED SCALABLE, FLEXIBLE DSP MEGAMODULE ARCHITECTURE
- Publication number 20170153890
- Publication date Jun 1, 2017
- TEXAS INSTRUMENTS INCORPORATED
- Timothy D. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USING L1 CACHE AS RE-ORDER BUFFER
- Publication number 20170010967
- Publication date Jan 12, 2017
- TEXAS INSTRUMENTS INCORPORATED
- Ramakrishnan Venkatasubramanian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ON-CHIP POWER-DOMAIN SUPPLY DROOPING FOR LOW VOLTAGE IDLE/STANDBY M...
- Publication number 20160357210
- Publication date Dec 8, 2016
- Michael Gill
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Power Switch with Source-Bias Mode for on-chip Powerdomain Supply D...
- Publication number 20160357211
- Publication date Dec 8, 2016
- TEXAS INSTRUMENTS INCORPORATED
- Ramakrishnan Venkatasubramanian
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Hiding Page Translation Miss Latency in Program Memory Controller B...
- Publication number 20160179700
- Publication date Jun 23, 2016
- TEXAS INSTRUMENTS INCORPORATED
- Ramakrishnan Venkatasubramanian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIDING PAGE TRANSLATION MISS LATENCY IN PROGRAM MEMORY CONTROLLER B...
- Publication number 20160179699
- Publication date Jun 23, 2016
- TEXAS INSTRUMENTS INCORPORATED
- Ramakrishnan Venkatasubramanian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Local Page Translation and Permissions Storage for the Page Window...
- Publication number 20160179695
- Publication date Jun 23, 2016
- TEXAS INSTRUMENTS INCORPORATED
- Oluleye Olorode
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USING L1 CACHE AS RE-ORDER BUFFER
- Publication number 20160019151
- Publication date Jan 21, 2016
- TEXAS INSTRUMENTS INCORPORATED
- Ramakrishnan Venkatasubramanian
- G06 - COMPUTING CALCULATING COUNTING

Ramakrishnan Venkatasubramanian

Person

Patents Grantslast 30 patents

Non-volatile memory compression for memory repair

Zero latency prefetching in caches

Servicing CPU demand requests with inflight prefetches

Highly integrated scalable, flexible DSP megamodule architecture

Electrical and logic isolation for systems on a chip

Integrated circuit with high-speed clock bypass before reset

Non-volatile memory compression for memory repair

Lookahead priority collection to support priority elevation

Servicing CPU demand requests with inflight prefetches

Zero latency prefetching in caches

Non-volatile memory compression for memory repair

Integrated circuit with high-speed clock bypass before reset

Highly integrated scalable, flexible DSP megamodule architecture

Zero latency prefetching in caches

Lookahead priority collection to support priority elevation

Servicing CPU demand requests with inflight prefetches

Servicing CPU demand requests with inflight prefetchs

Highly integrated scalable, flexible DSP megamodule architecture

Power switch with source-bias mode for on-chip powerdomain supply d...

Using L1 cache as re-order buffer

Hiding page translation miss latency in program memory controller b...

On-chip power-domain supply drooping for low voltage idle/standby m...

Highly integrated scalable, flexible DSP megamodule architecture

Protection of memories, datapath and pipeline registers, and other...

Local page translation and permissions storage for the page window...

Hiding page translation miss latency in program memory controller b...

Using L1 cache as re-order buffer

Power switch with source-bias mode for on-chip powerdomain supply d...

Reducing current leakage in L1 program memory

Asynchronous clock dividers to reduce on-chip variations of clock t...

Patents Applicationslast 30 patents

NON-VOLATILE MEMORY COMPRESSION FOR MEMORY REPAIR

ZERO LATENCY PREFETCHING IN CACHES

SERVICING CPU DEMAND REQUESTS WITH INFLIGHT PREFETCHES

PROCESSOR ARCHITECTURE WITH MEMORY ACCESS CIRCUIT

ELECTRICAL AND LOGIC ISOLATION FOR SYSTEMS ON A CHIP

NON-VOLATILE MEMORY COMPRESSION FOR MEMORY REPAIR

LOOKAHEAD PRIORITY COLLECTION TO SUPPORT PRIORITY ELEVATION

SERVICING CPU DEMAND REQUESTS WITH INFLIGHT PREFETCHES

ZERO LATENCY PREFETCHING IN CACHES

NON-VOLATILE MEMORY COMPRESSION FOR MEMORY REPAIR

NON-VOLATILE MEMORY COMPRESSION FOR MEMORY REPAIR

INTEGRATED CIRCUIT WITH HIGH-SPEED CLOCK BYPASS BEFORE RESET

HIGHLY INTEGRATED SCALABLE, FLEXIBLE DSP MEGAMODULE ARCHITECTURE

Electrical and Logic Isolation for Systems on a Chip

INTEGRATED CIRCUIT WITH HIGH-SPEED CLOCK BYPASS BEFORE RESET

ZERO LATENCY PREFETCHING IN CACHES

LOOKAHEAD PRIORITY COLLECTION TO SUPPORT PRIORITY ELEVATION

SERVICING CPU DEMAND REQUESTS WITH INFLIGHT PREFETCHES

SERVICING CPU DEMAND REQUESTS WITH INFLIGHT PREFETCHES

HIGHLY INTEGRATED SCALABLE, FLEXIBLE DSP MEGAMODULE ARCHITECTURE

ZERO LATENCY PREFETCHING IN CACHES

Lookahead Priority Collection to Support Priority Elevation

HIGHLY INTEGRATED SCALABLE, FLEXIBLE DSP MEGAMODULE ARCHITECTURE

USING L1 CACHE AS RE-ORDER BUFFER

ON-CHIP POWER-DOMAIN SUPPLY DROOPING FOR LOW VOLTAGE IDLE/STANDBY M...

Power Switch with Source-Bias Mode for on-chip Powerdomain Supply D...

Hiding Page Translation Miss Latency in Program Memory Controller B...

HIDING PAGE TRANSLATION MISS LATENCY IN PROGRAM MEMORY CONTROLLER B...

Local Page Translation and Permissions Storage for the Page Window...

USING L1 CACHE AS RE-ORDER BUFFER