Raman Nayyar

Person

Hillsboro, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for memory write performance optimization in a...
- Patent number 8,990,456
- Issue date Mar 24, 2015
- Intel Corporation
- Raman Nayyar
- G10 - MUSICAL INSTRUMENTS ACOUSTICS
Information Patent Grant
Method and apparatus for memory write performance optimization in a...
- Patent number 8,341,360
- Issue date Dec 25, 2012
- Intel Corporation
- Raman Nayyar
- G10 - MUSICAL INSTRUMENTS ACOUSTICS
Information Patent Grant
Method and apparatus for exploiting parallelism across multiple tra...
- Patent number 7,562,194
- Issue date Jul 14, 2009
- Intel Corporation
- Raman Nayyar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transaction flow and ordering for a packet processing engine, locat...
- Patent number 7,487,284
- Issue date Feb 3, 2009
- Intel Corporation
- Suvansh Krishan Kapur
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
System and method for thermal throttling of memory modules
- Patent number 7,318,130
- Issue date Jan 8, 2008
- Intel Corporation
- Warren R. Morrow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphics address relocation table (GART) stored entirely in a local...
- Patent number 6,618,770
- Issue date Sep 9, 2003
- Intel Corporation
- Raman Nayyar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphics address relocation table (GART) stored entirely in a local...
- Patent number 6,457,068
- Issue date Sep 24, 2002
- Intel Corporation
- Raman Nayyar
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Method and Apparatus for Memory Write Performance Optimization in A...
- Publication number 20150006825
- Publication date Jan 1, 2015
- Intel Corporation
- Raman Nayyar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Memory Write Performance Optimization in A...
- Publication number 20130212336
- Publication date Aug 15, 2013
- Intel Corporation
- Raman Nayyar
- G10 - MUSICAL INSTRUMENTS ACOUSTICS
Information Patent Application
Method and Apparatus for Exploiting Parallelism Across Multiple Tra...
- Publication number 20090254714
- Publication date Oct 8, 2009
- Intel Corporation
- Raman Nayyar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Transaction flow and ordering for a packet processing engine, loca...
- Publication number 20080025289
- Publication date Jan 31, 2008
- Suvansh Krishan Kapur
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method and apparatus for exploiting parallelism across multiple tra...
- Publication number 20070186060
- Publication date Aug 9, 2007
- Raman Nayyar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for memory write performance optimization in a...
- Publication number 20070156980
- Publication date Jul 5, 2007
- Raman Nayyar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for thermal throttling of memory modules
- Publication number 20050289292
- Publication date Dec 29, 2005
- Warren R. Morrow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Input/output (I/O) address translation in a bridge proximate to a l...
- Publication number 20020129187
- Publication date Sep 12, 2002
- Raman Nayyar
- G06 - COMPUTING CALCULATING COUNTING

Raman Nayyar

Person

Patents Grantslast 30 patents

Method and apparatus for memory write performance optimization in a...

Method and apparatus for memory write performance optimization in a...

Method and apparatus for exploiting parallelism across multiple tra...

Transaction flow and ordering for a packet processing engine, locat...

System and method for thermal throttling of memory modules

Graphics address relocation table (GART) stored entirely in a local...

Graphics address relocation table (GART) stored entirely in a local...

Patents Applicationslast 30 patents

Method and Apparatus for Memory Write Performance Optimization in A...

Method and Apparatus for Memory Write Performance Optimization in A...

Method and Apparatus for Exploiting Parallelism Across Multiple Tra...

Transaction flow and ordering for a packet processing engine, loca...

Method and apparatus for exploiting parallelism across multiple tra...

Method and apparatus for memory write performance optimization in a...

System and method for thermal throttling of memory modules

Input/output (I/O) address translation in a bridge proximate to a l...