Ramanand Venkata

Person

Fremont, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Configuration via high speed serial link
- Patent number 10,649,944
- Issue date May 12, 2020
- Altera Corporation
- Ramanand Venkata
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock grid for integrated circuit
- Patent number 9,843,332
- Issue date Dec 12, 2017
- Altera Corporation
- Ramanand Venkata
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Configuration via high speed serial link
- Patent number 9,690,741
- Issue date Jun 27, 2017
- Altera Corporation
- Ramanand Venkata
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock grid for integrated circuit
- Patent number 9,660,630
- Issue date May 23, 2017
- Altera Corporation
- Ramanand Venkata
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Configurable clock grid structures
- Patent number 9,606,573
- Issue date Mar 28, 2017
- Altera Corporation
- Carl Ebeling
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuits with clock selection circuitry
- Patent number 9,515,880
- Issue date Dec 6, 2016
- Altera Corporation
- Ramanand Venkata
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Clock grid for integrated circuit
- Patent number 9,503,057
- Issue date Nov 22, 2016
- Altera Corporation
- Ramanand Venkata
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock grid for integrated circuit
- Patent number 9,473,112
- Issue date Oct 18, 2016
- Altera Corporation
- Ramanand Venkata
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital phase locked loop circuitry and methods
- Patent number 9,438,272
- Issue date Sep 6, 2016
- Altera Corporation
- Ramanand Venkata
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Serializer circuitry for high-speed serial data transmitters on pro...
- Patent number 9,077,330
- Issue date Jul 7, 2015
- Altera Corporation
- Toan Thanh Nguyen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Programmable matrix for the allocation of communication resources
- Patent number 9,077,341
- Issue date Jul 7, 2015
- Altera Corporation
- Catherine Chingi Chang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Techniques for providing clock signals in an integrated circuit
- Patent number 9,024,673
- Issue date May 5, 2015
- Altera Corporation
- Ramanand Venkata
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for aligning and reducing skew in serial data signals
- Patent number 8,994,425
- Issue date Mar 31, 2015
- Altera Corporation
- Ramanand Venkata
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuitry for padded communication protocols
- Patent number 8,923,440
- Issue date Dec 30, 2014
- Altera Corporation
- Ramanand Venkata
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Apparatus and methods for low-skew channel bonding
- Patent number 8,812,893
- Issue date Aug 19, 2014
- Altera Corporation
- Ramanand Venkata
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital phase locked loop circuitry and methods
- Patent number 8,804,890
- Issue date Aug 12, 2014
- Altera Corporation
- Ramanand Venkata
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Transceiver circuitry with multiple phase-locked loops
- Patent number 8,692,595
- Issue date Apr 8, 2014
- Altera Corporation
- David W. Mendel
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Techniques for providing clock signals in clock networks
- Patent number 8,581,653
- Issue date Nov 12, 2013
- Altera Corporation
- Victor Maruri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and methods for serial interfaces with shared datapaths
- Patent number 8,571,059
- Issue date Oct 29, 2013
- Altera Corporation
- Arch Zaliznyak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Serializer circuitry for high-speed serial data transmitters on pro...
- Patent number 8,570,197
- Issue date Oct 29, 2013
- Altera Corporation
- Toan Thanh Nguyen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Digital phase locked loop circuitry and methods
- Patent number 8,462,908
- Issue date Jun 11, 2013
- Altera Corporation
- Ramanand Venkata
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Digital phase locked loop circuitry and methods
- Patent number 7,869,553
- Issue date Jan 11, 2011
- Altera Corporation
- Ramanand Venkata
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Serializer circuitry for high-speed serial data transmitters on pro...
- Patent number 7,848,318
- Issue date Dec 7, 2010
- Altera Corporation
- Toan Thanh Nguyen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multiple data rates in integrated circuit device serial interface
- Patent number 7,698,482
- Issue date Apr 13, 2010
- Altera Corporation
- Ramanand Venkata
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Deserializer circuitry for high-speed serial data receivers on prog...
- Patent number 7,659,838
- Issue date Feb 9, 2010
- Altera Corporation
- Toan Thanh Nguyen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multi-channel communication circuitry for programmable logic device...
- Patent number 7,656,187
- Issue date Feb 2, 2010
- Altera Corporation
- Thungoc Tran
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device with serial interconnect
- Patent number 7,646,217
- Issue date Jan 12, 2010
- Altera Corporation
- Ramanand Venkata
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic devices with multi-standard byte synchronization...
- Patent number 7,577,166
- Issue date Aug 18, 2009
- Altera Corporation
- Ramanand Venkata
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multiple data rates in programmable logic device serial interface
- Patent number 7,538,578
- Issue date May 26, 2009
- Altera Corporation
- Ramanand Venkata
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuitry for padded communication protocols
- Patent number 7,443,922
- Issue date Oct 28, 2008
- Altera Corporation
- Ramanand Venkata
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
CONFIGURATION VIA HIGH SPEED SERIAL LINK
- Publication number 20210011875
- Publication date Jan 14, 2021
- Altera Corporation
- Ramanand Venkata
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURATION VIA HIGH SPEED SERIAL LINK
- Publication number 20170357606
- Publication date Dec 14, 2017
- Altera Corporation
- Ramanand Venkata
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURATION VIA HIGH SPEED SERIAL LINK
- Publication number 20150019777
- Publication date Jan 15, 2015
- Altera Corporation
- Ramanand Venkata
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Techniques for Aligning and Reducing Skew in Serial Data Signals
- Publication number 20140035642
- Publication date Feb 6, 2014
- Altera Corporation
- Ramanand Venkata
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SERIALIZER CIRCUITRY FOR HIGH-SPEED SERIAL DATA TRANSMITTERS ON PRO...
- Publication number 20140009188
- Publication date Jan 9, 2014
- Altera Corporation
- Toan Thanh Nguyen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
DIGITAL PHASE LOCKED LOOP CIRCUITRY AND METHODS
- Publication number 20130265179
- Publication date Oct 10, 2013
- Ramanand Venkata
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
DIGITAL PHASE LOCKED LOOP CIRCUITRY AND METHODS
- Publication number 20110090101
- Publication date Apr 21, 2011
- Ramanand Venkata
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SERIALIZER CIRCUITRY FOR HIGH-SPEED SERIAL DATA TRANSMITTERS ON PRO...
- Publication number 20110068845
- Publication date Mar 24, 2011
- Toan Thanh Nguyen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PROGRAMMABLE LOGIC DEVICE WITH SERIAL INTERCONNECT
- Publication number 20070188189
- Publication date Aug 16, 2007
- Altera Corporation
- Ramanand Venkata
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Next generation 8B10B architecture
- Publication number 20070139232
- Publication date Jun 21, 2007
- Altera Corporation
- Ramanand Venkata
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multi-channel communication circuitry for programmable logic device...
- Publication number 20070058618
- Publication date Mar 15, 2007
- Altera Corporation
- Thungoc Tran
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Deserializer circuitry for high-speed serial data receivers on prog...
- Publication number 20070043991
- Publication date Feb 22, 2007
- Altera Corporation
- Toan Thanh Nguyen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Serializer circuitry for high-speed serial data transmitters on pro...
- Publication number 20070030184
- Publication date Feb 8, 2007
- Altera Corporation
- Toan Thanh Nguyen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Multiple data rates in programmable logic device serial interface
- Publication number 20070011370
- Publication date Jan 11, 2007
- Ramanand Venkata
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Multiple data rates in programmable logic device serial interface
- Publication number 20060233172
- Publication date Oct 19, 2006
- Ramanand Venkata
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Next generation 8B10B architecture
- Publication number 20060095613
- Publication date May 4, 2006
- Altera Corporation
- Ramanand Venkata
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Programmable logic devices with multi-standard byte synchronization...
- Publication number 20060012394
- Publication date Jan 19, 2006
- Altera Corporation
- Ramanand Venkata
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Programmable logic devices with multi-standard byte synchronization...
- Publication number 20050007996
- Publication date Jan 13, 2005
- Altera Corporation
- Ramanand Venkata
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Digital phase locked loop circuitry and methods
- Publication number 20040140837
- Publication date Jul 22, 2004
- Altera Corporation
- Ramanand Venkata
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Programmable logic devices with multi-standard byte synchronization...
- Publication number 20030052709
- Publication date Mar 20, 2003
- Altera Corporation
- Ramanand Venkata
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Ramanand Venkata

Person

Patents Grantslast 30 patents

Configuration via high speed serial link

Clock grid for integrated circuit

Configuration via high speed serial link

Clock grid for integrated circuit

Configurable clock grid structures

Integrated circuits with clock selection circuitry

Clock grid for integrated circuit

Clock grid for integrated circuit

Digital phase locked loop circuitry and methods

Serializer circuitry for high-speed serial data transmitters on pro...

Programmable matrix for the allocation of communication resources

Techniques for providing clock signals in an integrated circuit

Techniques for aligning and reducing skew in serial data signals

Circuitry for padded communication protocols

Apparatus and methods for low-skew channel bonding

Digital phase locked loop circuitry and methods

Transceiver circuitry with multiple phase-locked loops

Techniques for providing clock signals in clock networks

Apparatus and methods for serial interfaces with shared datapaths

Serializer circuitry for high-speed serial data transmitters on pro...

Digital phase locked loop circuitry and methods

Digital phase locked loop circuitry and methods

Serializer circuitry for high-speed serial data transmitters on pro...

Multiple data rates in integrated circuit device serial interface

Deserializer circuitry for high-speed serial data receivers on prog...

Multi-channel communication circuitry for programmable logic device...

Programmable logic device with serial interconnect

Programmable logic devices with multi-standard byte synchronization...

Multiple data rates in programmable logic device serial interface

Circuitry for padded communication protocols

Patents Applicationslast 30 patents

CONFIGURATION VIA HIGH SPEED SERIAL LINK

CONFIGURATION VIA HIGH SPEED SERIAL LINK

CONFIGURATION VIA HIGH SPEED SERIAL LINK

Techniques for Aligning and Reducing Skew in Serial Data Signals

SERIALIZER CIRCUITRY FOR HIGH-SPEED SERIAL DATA TRANSMITTERS ON PRO...

DIGITAL PHASE LOCKED LOOP CIRCUITRY AND METHODS

DIGITAL PHASE LOCKED LOOP CIRCUITRY AND METHODS

SERIALIZER CIRCUITRY FOR HIGH-SPEED SERIAL DATA TRANSMITTERS ON PRO...

PROGRAMMABLE LOGIC DEVICE WITH SERIAL INTERCONNECT

Next generation 8B10B architecture

Multi-channel communication circuitry for programmable logic device...

Deserializer circuitry for high-speed serial data receivers on prog...

Serializer circuitry for high-speed serial data transmitters on pro...

Multiple data rates in programmable logic device serial interface

Multiple data rates in programmable logic device serial interface

Next generation 8B10B architecture

Programmable logic devices with multi-standard byte synchronization...

Programmable logic devices with multi-standard byte synchronization...

Digital phase locked loop circuitry and methods

Programmable logic devices with multi-standard byte synchronization...