Ramaswamy Ranganathan

Person

Saratoga, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Enhanced pad design for solder attach devices
- Patent number 8,163,643
- Issue date Apr 24, 2012
- Linear Technology Corporation
- Maurice O. Othieno
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Eliminate IMC cracking in post wirebonded dies: macro level stress...
- Patent number 7,531,442
- Issue date May 12, 2009
- LSI Corporation
- Jayanthi Pallinti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Test structure for detecting bonding-induced cracks
- Patent number 6,998,638
- Issue date Feb 14, 2006
- LSI Logic Corporation
- Qwai H. Low
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Insulated bonding wire tool for microelectronic packaging
- Patent number 6,991,147
- Issue date Jan 31, 2006
- LSI Logic Corporation
- Chok J. Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dielectric stack
- Patent number 6,963,138
- Issue date Nov 8, 2005
- LSI Logic Corporation
- Qwai H. Low
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Test structure
- Patent number 6,861,748
- Issue date Mar 1, 2005
- LSI Logic Corporation
- Qwai H. Low
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Buffer metal layer
- Patent number 6,861,343
- Issue date Mar 1, 2005
- Chok J. Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Slotted bonding pad
- Patent number 6,825,563
- Issue date Nov 30, 2004
- LSI Logic Corporation
- Ramaswamy Ranganathan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bonding pad for low k dielectric
- Patent number 6,798,035
- Issue date Sep 28, 2004
- LSI Logic Corporation
- Qwai H. Low
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Test structure for detecting bonding-induced cracks
- Patent number 6,781,150
- Issue date Aug 24, 2004
- LSI Logic Corporation
- Qwai H. Low
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bonding pad isolation
- Patent number 6,743,979
- Issue date Jun 1, 2004
- LSI Logic Corporation
- Michael J. Berman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Insulated bonding wire for microelectronic packaging
- Patent number 6,670,214
- Issue date Dec 30, 2003
- LSI Logic Corporation
- Chok J. Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit having dedicated probe pads for use in testing d...
- Patent number 6,573,113
- Issue date Jun 3, 2003
- LSI Logic Corporation
- Qwai H. Low
- G01 - MEASURING TESTING
Information Patent Grant
Tape design to reduce warpage
- Patent number 6,486,002
- Issue date Nov 26, 2002
- LSI Logic Corporation
- Qwai H. Low
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for assembling tape ball grid arrays
- Patent number 6,425,179
- Issue date Jul 30, 2002
- LSI Logic Corporation
- Qwai H. Low
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multiple row wire bonding with ball bonds of outer bond pads bonded...
- Patent number 6,329,278
- Issue date Dec 11, 2001
- LSI Logic Corporation
- Qwai H. Low
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor flip chip ball grid array package
- Patent number 6,266,249
- Issue date Jul 24, 2001
- LSI Logic Corporation
- Kishor V. Desai
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Eliminate IMC cracking in post wirebonded dies: macro level stress...
- Publication number 20070123024
- Publication date May 31, 2007
- LSI Logic Corporation
- Jayanthi Pallinti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Test structure for detecting bonding-induced cracks
- Publication number 20040217487
- Publication date Nov 4, 2004
- Qwai H. Low
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Insulated bonding wire tool for microelectronic packaging
- Publication number 20040182911
- Publication date Sep 23, 2004
- Chok J. Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Wire bonding to full array bonding pads on active circuitry
- Publication number 20040178498
- Publication date Sep 16, 2004
- Qwai H. Low
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dielectric stack
- Publication number 20040150069
- Publication date Aug 5, 2004
- Qwai H. Low
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Test structure
- Publication number 20040096995
- Publication date May 20, 2004
- Qwai H. Low
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Buffer metal layer
- Publication number 20040072414
- Publication date Apr 15, 2004
- Chok J. Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Controlled impedance for wire bonding interconnects
- Publication number 20040070065
- Publication date Apr 15, 2004
- Aritharan Thurairajaratnam
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Test structure
- Publication number 20040043656
- Publication date Mar 4, 2004
- Qwai H. Low
- H01 - BASIC ELECTRIC ELEMENTS

Ramaswamy Ranganathan

Person

Patents Grantslast 30 patents

Enhanced pad design for solder attach devices

Eliminate IMC cracking in post wirebonded dies: macro level stress...

Test structure for detecting bonding-induced cracks

Insulated bonding wire tool for microelectronic packaging

Dielectric stack

Test structure

Buffer metal layer

Slotted bonding pad

Bonding pad for low k dielectric

Test structure for detecting bonding-induced cracks

Bonding pad isolation

Insulated bonding wire for microelectronic packaging

Integrated circuit having dedicated probe pads for use in testing d...

Tape design to reduce warpage

Method for assembling tape ball grid arrays

Multiple row wire bonding with ball bonds of outer bond pads bonded...

Semiconductor flip chip ball grid array package

Patents Applicationslast 30 patents

Eliminate IMC cracking in post wirebonded dies: macro level stress...

Test structure for detecting bonding-induced cracks

Insulated bonding wire tool for microelectronic packaging

Wire bonding to full array bonding pads on active circuitry

Dielectric stack

Test structure

Buffer metal layer

Controlled impedance for wire bonding interconnects

Test structure