Ramesh C. Tekumalla

Person

Breinigsville, PA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Instruction address encoding and decoding based on program construc...
- Patent number 9,348,593
- Issue date May 24, 2016
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Prakash Krishnamoorthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated clock architecture for improved testing
- Patent number 9,251,916
- Issue date Feb 2, 2016
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Ramesh C. Tekumalla
- G11 - INFORMATION STORAGE
Information Patent Grant
At-speed scan testing of interface functional logic of an embedded...
- Patent number 8,924,801
- Issue date Dec 30, 2014
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit having clock gating circuitry responsive to scan...
- Patent number 8,904,255
- Issue date Dec 2, 2014
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Grant
At-speed scan testing of clock divider logic in a clock module of a...
- Patent number 8,898,527
- Issue date Nov 25, 2014
- LSI Corporation
- Priyesh Kumar
- G01 - MEASURING TESTING
Information Patent Grant
Scan enable timing control for testing of scan cells
- Patent number 8,850,280
- Issue date Sep 30, 2014
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Grant
Scan circuitry for testing input and output functional paths of an...
- Patent number 8,826,087
- Issue date Sep 2, 2014
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Grant
Scan test circuitry configured to prevent violation of multiplexer...
- Patent number 8,819,508
- Issue date Aug 26, 2014
- LSI Corporation
- Narendra B. Devta Prasanna
- G01 - MEASURING TESTING
Information Patent Grant
Dynamic clock domain bypass for scan chains
- Patent number 8,812,921
- Issue date Aug 19, 2014
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Grant
Clock control for reducing timing exceptions in scan testing of an...
- Patent number 8,799,731
- Issue date Aug 5, 2014
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit comprising scan test circuitry with parallel reo...
- Patent number 8,793,546
- Issue date Jul 29, 2014
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Grant
Scan chain lockup latch with data input control responsive to scan...
- Patent number 8,788,896
- Issue date Jul 22, 2014
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Grant
Scan test circuitry with selectable transition launch mode
- Patent number 8,751,884
- Issue date Jun 10, 2014
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Grant
Efficient wrapper cell design for scan testing of integrated
- Patent number 8,738,978
- Issue date May 27, 2014
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Grant
Scan test circuitry configured for bypassing selected segments of a...
- Patent number 8,726,108
- Issue date May 13, 2014
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Grant
Coding circuitry for difference-based data transformation
- Patent number 8,711,013
- Issue date Apr 29, 2014
- LSI Corporation
- Prakash Krishnamoorthy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Scan test circuitry configured to prevent capture of potentially no...
- Patent number 8,700,962
- Issue date Apr 15, 2014
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit with transition control circuitry for limiting s...
- Patent number 8,677,200
- Issue date Mar 18, 2014
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit comprising scan test circuitry with controllable...
- Patent number 8,671,320
- Issue date Mar 11, 2014
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Grant
Scan test circuitry with delay defect bypass functionality
- Patent number 8,645,778
- Issue date Feb 4, 2014
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Grant
Scan test circuitry comprising scan cells with multiple scan inputs
- Patent number 8,615,693
- Issue date Dec 24, 2013
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Grant
Low-power and area-efficient scan cell for integrated circuit testing
- Patent number 8,566,658
- Issue date Oct 22, 2013
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CIRCUIT COMPRISING TEST CIRCUITRY FOR TESTING FAN-OUT PA...
- Publication number 20140365838
- Publication date Dec 11, 2014
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Application
Method for Testing Paths to Pull-Up and Pull-Down of Input/Output Pads
- Publication number 20140304562
- Publication date Oct 9, 2014
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Application
Scan Chain Reconfiguration and Repair
- Publication number 20140298123
- Publication date Oct 2, 2014
- LSI Corporation
- Ramesh C. Tekumalla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrated Clock Architecture for Improved Testing
- Publication number 20140289550
- Publication date Sep 25, 2014
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Application
Local Repair Signature Handling for Repairable Memories
- Publication number 20140281703
- Publication date Sep 18, 2014
- LSI Corporation
- Ramesh C. Tekumalla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AT-SPEED SCAN TESTING OF INTERFACE FUNCTIONAL LOGIC OF AN EMBEDDED...
- Publication number 20140229778
- Publication date Aug 14, 2014
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Application
AT-SPEED SCAN TESTING OF CLOCK DIVIDER LOGIC IN A CLOCK MODULE OF A...
- Publication number 20140208175
- Publication date Jul 24, 2014
- LSI Corporation
- Priyesh Kumar
- G01 - MEASURING TESTING
Information Patent Application
SCAN TEST CIRCUITRY COMPRISING AT LEAST ONE SCAN CHAIN AND ASSOCIAT...
- Publication number 20140201584
- Publication date Jul 17, 2014
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Application
SCAN TEST CIRCUITRY WITH CONTROL CIRCUITRY CONFIGURED TO SUPPORT A...
- Publication number 20140149812
- Publication date May 29, 2014
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Application
SCAN CIRCUITRY FOR TESTING INPUT AND OUTPUT FUNCTIONAL PATHS OF AN...
- Publication number 20140143621
- Publication date May 22, 2014
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Application
SCAN TEST CIRCUITRY CONFIGURED TO PREVENT VIOLATION OF MULTIPLEXER...
- Publication number 20140101501
- Publication date Apr 10, 2014
- LSI Corporation
- Narendra B. Devta Prasanna
- G01 - MEASURING TESTING
Information Patent Application
CLOCK CONTROL FOR REDUCING TIMING EXCEPTIONS IN SCAN TESTING OF AN...
- Publication number 20140101505
- Publication date Apr 10, 2014
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Application
INSTRUCTION ADDRESS ENCODING AND DECODING BASED ON PROGRAM CONSTRUC...
- Publication number 20140068229
- Publication date Mar 6, 2014
- LSI Corporation
- Prakash Krishnamoorthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCAN TEST CIRCUITRY CONFIGURED TO PREVENT CAPTURE OF POTENTIALLY NO...
- Publication number 20140032985
- Publication date Jan 30, 2014
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Application
SCAN CONTROLLER CONFIGURED TO CONTROL SIGNAL VALUES APPLIED TO SIGN...
- Publication number 20130311843
- Publication date Nov 21, 2013
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Application
SCAN TEST CIRCUITRY WITH SELECTABLE TRANSITION LAUNCH MODE
- Publication number 20130290799
- Publication date Oct 31, 2013
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Application
SCAN-BASED CAPTURE AND SHIFT OF INTERFACE FUNCTIONAL SIGNAL VALUES...
- Publication number 20130275824
- Publication date Oct 17, 2013
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT HAVING CLOCK GATING CIRCUITRY RESPONSIVE TO SCAN...
- Publication number 20130219238
- Publication date Aug 22, 2013
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Application
CODING CIRCUITRY FOR DIFFERENCE-BASED DATA TRANSFORMATION
- Publication number 20130181852
- Publication date Jul 18, 2013
- LSI Corporation
- Prakash Krishnamoorthy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SCAN TEST CIRCUITRY CONFIGURED FOR BYPASSING SELECTED SEGMENTS OF A...
- Publication number 20130185607
- Publication date Jul 18, 2013
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Application
SCAN CHAIN LOCKUP LATCH WITH DATA INPUT CONTROL RESPONSIVE TO SCAN...
- Publication number 20130179742
- Publication date Jul 11, 2013
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Application
Scan Test Circuitry with Delay Defect Bypass Functionality
- Publication number 20130173976
- Publication date Jul 4, 2013
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Application
DIVIDER CIRCUITRY WITH QUOTIENT PREDICTION BASED ON ESTIMATED PARTI...
- Publication number 20130124594
- Publication date May 16, 2013
- LSI Corporation
- Prakash Krishnamoorthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCAN ENABLE TIMING CONTROL FOR TESTING OF SCAN CELLS
- Publication number 20130111286
- Publication date May 2, 2013
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Application
DYNAMIC CLOCK DOMAIN BYPASS FOR SCAN CHAINS
- Publication number 20130103994
- Publication date Apr 25, 2013
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT WITH TRANSITION CONTROL CIRCUITRY FOR LIMITING S...
- Publication number 20130067290
- Publication date Mar 14, 2013
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Application
Scan Test Circuitry Comprising Scan Cells with Multiple Scan Inputs
- Publication number 20130055041
- Publication date Feb 28, 2013
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Application
EFFICIENT WRAPPER CELL DESIGN FOR SCAN TESTING OF INTEGRATED CIRCUITS
- Publication number 20130007547
- Publication date Jan 3, 2013
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT COMPRISING SCAN TEST CIRCUITRY WITH CONTROLLABLE...
- Publication number 20120331362
- Publication date Dec 27, 2012
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT COMPRISING SCAN TEST CIRCUITRY WITH PARALLEL REO...
- Publication number 20120324303
- Publication date Dec 20, 2012
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING

Ramesh C. Tekumalla

Person

Patents Grantslast 30 patents

Instruction address encoding and decoding based on program construc...

Integrated clock architecture for improved testing

At-speed scan testing of interface functional logic of an embedded...

Integrated circuit having clock gating circuitry responsive to scan...

At-speed scan testing of clock divider logic in a clock module of a...

Scan enable timing control for testing of scan cells

Scan circuitry for testing input and output functional paths of an...

Scan test circuitry configured to prevent violation of multiplexer...

Dynamic clock domain bypass for scan chains

Clock control for reducing timing exceptions in scan testing of an...

Integrated circuit comprising scan test circuitry with parallel reo...

Scan chain lockup latch with data input control responsive to scan...

Scan test circuitry with selectable transition launch mode

Efficient wrapper cell design for scan testing of integrated

Scan test circuitry configured for bypassing selected segments of a...

Coding circuitry for difference-based data transformation

Scan test circuitry configured to prevent capture of potentially no...

Integrated circuit with transition control circuitry for limiting s...

Integrated circuit comprising scan test circuitry with controllable...

Scan test circuitry with delay defect bypass functionality

Scan test circuitry comprising scan cells with multiple scan inputs

Low-power and area-efficient scan cell for integrated circuit testing

Patents Applicationslast 30 patents

INTEGRATED CIRCUIT COMPRISING TEST CIRCUITRY FOR TESTING FAN-OUT PA...

Method for Testing Paths to Pull-Up and Pull-Down of Input/Output Pads

Scan Chain Reconfiguration and Repair

Integrated Clock Architecture for Improved Testing

Local Repair Signature Handling for Repairable Memories

AT-SPEED SCAN TESTING OF INTERFACE FUNCTIONAL LOGIC OF AN EMBEDDED...

AT-SPEED SCAN TESTING OF CLOCK DIVIDER LOGIC IN A CLOCK MODULE OF A...

SCAN TEST CIRCUITRY COMPRISING AT LEAST ONE SCAN CHAIN AND ASSOCIAT...

SCAN TEST CIRCUITRY WITH CONTROL CIRCUITRY CONFIGURED TO SUPPORT A...

SCAN CIRCUITRY FOR TESTING INPUT AND OUTPUT FUNCTIONAL PATHS OF AN...

SCAN TEST CIRCUITRY CONFIGURED TO PREVENT VIOLATION OF MULTIPLEXER...

CLOCK CONTROL FOR REDUCING TIMING EXCEPTIONS IN SCAN TESTING OF AN...

INSTRUCTION ADDRESS ENCODING AND DECODING BASED ON PROGRAM CONSTRUC...

SCAN TEST CIRCUITRY CONFIGURED TO PREVENT CAPTURE OF POTENTIALLY NO...

SCAN CONTROLLER CONFIGURED TO CONTROL SIGNAL VALUES APPLIED TO SIGN...

SCAN TEST CIRCUITRY WITH SELECTABLE TRANSITION LAUNCH MODE

SCAN-BASED CAPTURE AND SHIFT OF INTERFACE FUNCTIONAL SIGNAL VALUES...

INTEGRATED CIRCUIT HAVING CLOCK GATING CIRCUITRY RESPONSIVE TO SCAN...

CODING CIRCUITRY FOR DIFFERENCE-BASED DATA TRANSFORMATION

SCAN TEST CIRCUITRY CONFIGURED FOR BYPASSING SELECTED SEGMENTS OF A...

SCAN CHAIN LOCKUP LATCH WITH DATA INPUT CONTROL RESPONSIVE TO SCAN...

Scan Test Circuitry with Delay Defect Bypass Functionality

DIVIDER CIRCUITRY WITH QUOTIENT PREDICTION BASED ON ESTIMATED PARTI...

SCAN ENABLE TIMING CONTROL FOR TESTING OF SCAN CELLS

DYNAMIC CLOCK DOMAIN BYPASS FOR SCAN CHAINS

INTEGRATED CIRCUIT WITH TRANSITION CONTROL CIRCUITRY FOR LIMITING S...

Scan Test Circuitry Comprising Scan Cells with Multiple Scan Inputs

EFFICIENT WRAPPER CELL DESIGN FOR SCAN TESTING OF INTEGRATED CIRCUITS

INTEGRATED CIRCUIT COMPRISING SCAN TEST CIRCUITRY WITH CONTROLLABLE...

INTEGRATED CIRCUIT COMPRISING SCAN TEST CIRCUITRY WITH PARALLEL REO...