Ramesh Gunna

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Scalable cache coherency protocol
- Patent number 11,947,457
- Issue date Apr 2, 2024
- Apple Inc.
- James Vash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable system on a chip
- Patent number 11,934,313
- Issue date Mar 19, 2024
- Apple Inc.
- Per H. Hammarlund
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable cache coherency protocol
- Patent number 11,868,258
- Issue date Jan 9, 2024
- Apple Inc.
- James Vash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power sense correction for power budget estimator
- Patent number 11,675,409
- Issue date Jun 13, 2023
- Apple Inc.
- Matthias Knoth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable cache coherency protocol
- Patent number 11,544,193
- Issue date Jan 3, 2023
- Apple Inc.
- James Vash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power sense correction for power budget estimator
- Patent number 11,416,056
- Issue date Aug 16, 2022
- Apple Inc.
- Matthias Knoth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive thermal control system
- Patent number 11,347,198
- Issue date May 31, 2022
- Apple Inc.
- Matthias Knoth
- G05 - CONTROLLING REGULATING
Information Patent Grant
Fetch predition circuit for reducing power consumption in a processor
- Patent number 10,901,484
- Issue date Jan 26, 2021
- Apple Inc.
- Conrado Blasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for reducing capacitor-induced noise
- Patent number 10,416,692
- Issue date Sep 17, 2019
- Apple Inc.
- Jong-Suk Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing power state in one power domain based on power states in a...
- Patent number 10,410,688
- Issue date Sep 10, 2019
- Apple Inc.
- Shih-Chieh Wen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Single power plane dynamic voltage margin recovery for multiple clo...
- Patent number 10,401,938
- Issue date Sep 3, 2019
- Apple Inc.
- Jong-Suk Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing power consumption in a processor
- Patent number 10,241,557
- Issue date Mar 26, 2019
- Apple Inc.
- Conrado Blasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing power state in one power domain based on power states in a...
- Patent number 10,147,464
- Issue date Dec 4, 2018
- Apple Inc.
- Shih-Chieh Wen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
IT instruction pre-decode
- Patent number 9,626,185
- Issue date Apr 18, 2017
- Apple Inc.
- Shyam Sundar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Next fetch predictor return address stack
- Patent number 9,405,544
- Issue date Aug 2, 2016
- Apple Inc.
- Douglas C. Holman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fetch width predictor
- Patent number 9,367,471
- Issue date Jun 14, 2016
- Apple Inc.
- Conrado Blasco-Allue
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Maintaining the integrity of an execution return address stack
- Patent number 9,354,886
- Issue date May 31, 2016
- Apple Inc.
- Ramesh B. Gunna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Lookahead scanning and cracking of microcode instructions in a disp...
- Patent number 9,280,352
- Issue date Mar 8, 2016
- Apple Inc.
- Ramesh B. Gunna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Preventing update training of first predictor with mismatching seco...
- Patent number 8,959,320
- Issue date Feb 17, 2015
- Apple Inc.
- Andrew J. Beaumont-Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Store handling in a processor
- Patent number 8,892,841
- Issue date Nov 18, 2014
- Apple Inc.
- Ramesh Gunna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Combining write buffer with dynamically adjustable flush metrics
- Patent number 8,566,528
- Issue date Oct 22, 2013
- Apple Inc.
- Peter J. Bannon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Indirect branch target predictor that prevents speculation if mispr...
- Patent number 8,555,040
- Issue date Oct 8, 2013
- Apple Inc.
- Andrew J. Beaumont-Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Converting victim writeback to a fill
- Patent number 8,364,907
- Issue date Jan 29, 2013
- Apple Inc.
- Ramesh Gunna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Retry mechanism
- Patent number 8,359,414
- Issue date Jan 22, 2013
- Apple Inc.
- James B. Keller
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Combining write buffer with dynamically adjustable flush metrics
- Patent number 8,352,685
- Issue date Jan 8, 2013
- Apple Inc.
- Peter J. Bannon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Latency reduction for cache coherent bus-based cache
- Patent number 8,347,040
- Issue date Jan 1, 2013
- Apple Inc.
- Brian P. Lilly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
R and C bit update handling
- Patent number 8,341,379
- Issue date Dec 25, 2012
- Apple Inc.
- Jesse Pan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data cache block zero implementation
- Patent number 8,301,843
- Issue date Oct 30, 2012
- Apple Inc.
- Ramesh Gunna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Replay reduction for power saving
- Patent number 8,255,670
- Issue date Aug 28, 2012
- Apple Inc.
- Po-Yung Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Store handling in a processor
- Patent number 8,239,638
- Issue date Aug 7, 2012
- Apple Inc.
- Ramesh Gunna
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Scalable System on a Chip
- Publication number 20240370371
- Publication date Nov 7, 2024
- Apple Inc.
- Per H. Hammarlund
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scalable Cache Coherency Protocol
- Publication number 20240273024
- Publication date Aug 15, 2024
- Apple Inc.
- James Vash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scalable Cache Coherency Protocol
- Publication number 20230169003
- Publication date Jun 1, 2023
- Apple Inc.
- James Vash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scalable Cache Coherency Protocol
- Publication number 20230083397
- Publication date Mar 16, 2023
- Apple Inc.
- James Vash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scalable System on a Chip
- Publication number 20230056044
- Publication date Feb 23, 2023
- Apple Inc.
- Per H. Hammarlund
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Power Sense Correction for Power Budget Estimator
- Publication number 20220342471
- Publication date Oct 27, 2022
- Apple Inc.
- Matthias Knoth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Power Sense Correction for Power Budget Estimator
- Publication number 20220091649
- Publication date Mar 24, 2022
- Apple Inc.
- Matthias Knoth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scalable Cache Coherency Protocol
- Publication number 20220083472
- Publication date Mar 17, 2022
- Apple Inc.
- James Vash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Adaptive Thermal Control System
- Publication number 20220075343
- Publication date Mar 10, 2022
- Apple Inc.
- Matthias Knoth
- G05 - CONTROLLING REGULATING
Information Patent Application
REDUCING POWER CONSUMPTION IN A PROCESSOR
- Publication number 20190286218
- Publication date Sep 19, 2019
- Apple Inc.
- Conrado Blasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Managing Power State in One Power Domain Based on Power States in A...
- Publication number 20190221241
- Publication date Jul 18, 2019
- Apple Inc.
- Shih-Chieh Wen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Reducing Capacitor-Induced Noise
- Publication number 20190086942
- Publication date Mar 21, 2019
- Apple Inc.
- Jong-Suk Lee
- G05 - CONTROLLING REGULATING
Information Patent Application
REDUCING POWER CONSUMPTION IN A PROCESSOR
- Publication number 20150169041
- Publication date Jun 18, 2015
- Apple Inc.
- Conrado Blasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NEXT FETCH PREDICTOR RETURN ADDRESS STACK
- Publication number 20140344558
- Publication date Nov 20, 2014
- Apple Inc.
- Douglas C. Holman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IT INSTRUCTION PRE-DECODE
- Publication number 20140244976
- Publication date Aug 28, 2014
- Apple Inc.
- Shyam Sundar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FETCH WIDTH PREDICTOR
- Publication number 20140075156
- Publication date Mar 13, 2014
- Conrado Blasco-Allue
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NEXT FETCH PREDICTOR TRAINING WITH HYSTERESIS
- Publication number 20130151823
- Publication date Jun 13, 2013
- Andrew J. Beaumont-Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MAINTAINING THE INTEGRITY OF AN EXECUTION RETURN ADDRESS STACK
- Publication number 20130138931
- Publication date May 30, 2013
- Ramesh B. Gunna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT MICROCODE INSTRUCTION DISPATCH
- Publication number 20130138924
- Publication date May 30, 2013
- Ramesh B. Gunna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Combining Write Buffer with Dynamically Adjustable Flush Metrics
- Publication number 20130103906
- Publication date Apr 25, 2013
- Apple Inc.
- Peter J. Bannon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Store Handling in a Processor
- Publication number 20120278685
- Publication date Nov 1, 2012
- Ramesh Gunna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Converting Victim Writeback to a Fill
- Publication number 20120131281
- Publication date May 24, 2012
- Ramesh Gunna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Combining Write Buffer with Dynamically Adjustable Flush Metrics
- Publication number 20120047332
- Publication date Feb 23, 2012
- Peter J. Bannon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Indirect Branch Target Predictor that Prevents Speculation if Mispr...
- Publication number 20110289300
- Publication date Nov 24, 2011
- Andrew J. Beaumont-Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Retry Mechanism
- Publication number 20110252165
- Publication date Oct 13, 2011
- James B. Keller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Latency Reduction for Cache Coherent Bus-Based Cache
- Publication number 20110197030
- Publication date Aug 11, 2011
- Brian P. Lilly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Converting Victim Writeback to a Fill
- Publication number 20110047336
- Publication date Feb 24, 2011
- Ramesh Gunna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Non-blocking Address Switch with Shallow Per Agent Queues
- Publication number 20100235675
- Publication date Sep 16, 2010
- Sridhar P. Subramanian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Fast L1 Flush Mechanism
- Publication number 20100235670
- Publication date Sep 16, 2010
- James B. Keller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
R and C Bit Update Handling
- Publication number 20100217951
- Publication date Aug 26, 2010
- Jesse Pan
- G06 - COMPUTING CALCULATING COUNTING

Ramesh Gunna

Person

Patents Grantslast 30 patents

Scalable cache coherency protocol

Scalable system on a chip

Scalable cache coherency protocol

Power sense correction for power budget estimator

Scalable cache coherency protocol

Power sense correction for power budget estimator

Adaptive thermal control system

Fetch predition circuit for reducing power consumption in a processor

Method and apparatus for reducing capacitor-induced noise

Managing power state in one power domain based on power states in a...

Single power plane dynamic voltage margin recovery for multiple clo...

Reducing power consumption in a processor

Managing power state in one power domain based on power states in a...

IT instruction pre-decode

Next fetch predictor return address stack

Fetch width predictor

Maintaining the integrity of an execution return address stack

Lookahead scanning and cracking of microcode instructions in a disp...

Preventing update training of first predictor with mismatching seco...

Store handling in a processor

Combining write buffer with dynamically adjustable flush metrics

Indirect branch target predictor that prevents speculation if mispr...

Converting victim writeback to a fill

Retry mechanism

Combining write buffer with dynamically adjustable flush metrics

Latency reduction for cache coherent bus-based cache

R and C bit update handling

Data cache block zero implementation

Replay reduction for power saving

Store handling in a processor

Patents Applicationslast 30 patents

Scalable System on a Chip

Scalable Cache Coherency Protocol

Scalable Cache Coherency Protocol

Scalable Cache Coherency Protocol

Scalable System on a Chip

Power Sense Correction for Power Budget Estimator

Power Sense Correction for Power Budget Estimator

Scalable Cache Coherency Protocol

Adaptive Thermal Control System

REDUCING POWER CONSUMPTION IN A PROCESSOR

Managing Power State in One Power Domain Based on Power States in A...

Method and Apparatus for Reducing Capacitor-Induced Noise

REDUCING POWER CONSUMPTION IN A PROCESSOR

NEXT FETCH PREDICTOR RETURN ADDRESS STACK

IT INSTRUCTION PRE-DECODE

FETCH WIDTH PREDICTOR

NEXT FETCH PREDICTOR TRAINING WITH HYSTERESIS

MAINTAINING THE INTEGRITY OF AN EXECUTION RETURN ADDRESS STACK

EFFICIENT MICROCODE INSTRUCTION DISPATCH

Combining Write Buffer with Dynamically Adjustable Flush Metrics

Store Handling in a Processor

Converting Victim Writeback to a Fill

Combining Write Buffer with Dynamically Adjustable Flush Metrics

Indirect Branch Target Predictor that Prevents Speculation if Mispr...

Retry Mechanism

Latency Reduction for Cache Coherent Bus-Based Cache

Converting Victim Writeback to a Fill

Non-blocking Address Switch with Shallow Per Agent Queues

Fast L1 Flush Mechanism

R and C Bit Update Handling