Ramesh Mahendra Pyndiah

Person

Brest, FR

People

Patents Grantslast 30 patents

Information Patent Grant
Method for transmitting a digital signal between at least two trans...
- Patent number 8,510,640
- Issue date Aug 13, 2013
- France Telecom
- Ramesh Pyndiah
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multiple-input-multiple-output transmission using non-binary LDPC c...
- Patent number 8,347,168
- Issue date Jan 1, 2013
- Fujitsu Limited
- Dai Kimura
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Construction of parity-check matrices for non-binarys LDPC codes
- Patent number 8,347,173
- Issue date Jan 1, 2013
- Fujitsu Limited
- Dai Kimura
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High-speed module, device and method for decoding a concatenated code
- Patent number 7,219,291
- Issue date May 15, 2007
- France Telecom
- Patrick Adde
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Process for transmitting information bits with error correction cod...
- Patent number 6,122,763
- Issue date Sep 19, 2000
- France Telecom
- Ramesh Pyndiah
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Process for transmitting information bits with error correction cod...
- Patent number 6,065,147
- Issue date May 16, 2000
- France Telecom
- Ramesh Pyndiah
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method for detecting information bits processed by concatenated blo...
- Patent number 5,563,897
- Issue date Oct 8, 1996
- France Telecom
- Ramesh Pyndiah
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
METHOD FOR TRANSMITTING A DIGITAL SIGNAL BETWEEN AT LEAST TWO TRANS...
- Publication number 20110161785
- Publication date Jun 30, 2011
- FRANCE TELECOM
- Ramesh Pyndiah
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
MULTIPLE-INPUT-MULTIPLE-OUTPUT TRANSMISSION USING NON-BINARY LDPC C...
- Publication number 20100107031
- Publication date Apr 29, 2010
- FUJITSU LIMITED
- Dai Kimura
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Construction of Parity-Check Matrices for Non-Binarys LDPC Codes
- Publication number 20090287981
- Publication date Nov 19, 2009
- Dai Kimura
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
High-speed module, device and method for decoding a concatenated code
- Publication number 20040054954
- Publication date Mar 18, 2004
- Patrick Adde
- H03 - BASIC ELECTRONIC CIRCUITRY

Ramesh Mahendra Pyndiah

Person

Patents Grantslast 30 patents

Method for transmitting a digital signal between at least two trans...

Multiple-input-multiple-output transmission using non-binary LDPC c...

Construction of parity-check matrices for non-binarys LDPC codes

High-speed module, device and method for decoding a concatenated code

Process for transmitting information bits with error correction cod...

Process for transmitting information bits with error correction cod...

Method for detecting information bits processed by concatenated blo...

Patents Applicationslast 30 patents

METHOD FOR TRANSMITTING A DIGITAL SIGNAL BETWEEN AT LEAST TWO TRANS...

MULTIPLE-INPUT-MULTIPLE-OUTPUT TRANSMISSION USING NON-BINARY LDPC C...

Construction of Parity-Check Matrices for Non-Binarys LDPC Codes

High-speed module, device and method for decoding a concatenated code