Ramesh Narayanaswamy

Person

Palo Alto, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Selective execution for partitioned parallel simulations
- Patent number 10,853,544
- Issue date Dec 1, 2020
- Synopsys, Inc.
- Ramesh Narayanaswamy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logic simulation and/or emulation which follows hardware semantics
- Patent number 10,423,740
- Issue date Sep 24, 2019
- Synopsys, Inc.
- Alexander Rabinovitch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Retiming a design for efficient parallel simulation
- Patent number 9,558,306
- Issue date Jan 31, 2017
- Synopsys, Inc.
- Ramesh Narayanaswamy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Quasi-dynamic scheduling and dynamic scheduling for efficient paral...
- Patent number 9,507,896
- Issue date Nov 29, 2016
- Synopsys, Inc.
- Ramesh Narayanaswamy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for delay immune and accelerated evaluation of digital circu...
- Patent number 8,359,186
- Issue date Jan 22, 2013
- Subbu Ganesan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable system for simulation and emulation of electronic circuits...
- Patent number 7,548,842
- Issue date Jun 16, 2009
- Eve S.A.
- Subbu Ganesan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compact processor element for a scalable digital logic verification...
- Patent number 7,509,602
- Issue date Mar 24, 2009
- Eve S.A.
- Subbu Ganesan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Functional verification system
- Patent number 6,691,287
- Issue date Feb 10, 2004
- Tharas Systems Inc.
- Subbu Ganesan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tracing the change of state of a signal in a functional verificatio...
- Patent number 6,629,297
- Issue date Sep 30, 2003
- Tharas Systems Inc.
- Subbu Ganesan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Run-time controller in a functional verification system
- Patent number 6,625,786
- Issue date Sep 23, 2003
- Tharas Systems, Inc.
- Subbu Ganesan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Functional verification of both cycle-based and non-cycle based des...
- Patent number 6,480,988
- Issue date Nov 12, 2002
- Tharas Systems, Inc.
- Subbu Ganesan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tracing different states reached by a signal in a functional verifi...
- Patent number 6,470,480
- Issue date Oct 22, 2002
- Tharas Systems, Inc.
- Subbu Ganesan
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MESSAGE PASSING MULTI PROCESSOR NETWORK FOR SIMULATION VECTOR PROCE...
- Publication number 20220253583
- Publication date Aug 11, 2022
- Synopsys, Inc.
- Subramanian GANESAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK AWARE SIMULATION VECTOR PROCESSOR
- Publication number 20220198120
- Publication date Jun 23, 2022
- Synopsys, Inc.
- Ramesh NARAYANASWAMY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Selective Execution For Partitioned Parallel Simulations
- Publication number 20170185700
- Publication date Jun 29, 2017
- Synopsys, Inc.
- Ramesh Narayanaswamy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
QUASI-DYNAMIC SCHEDULING AND DYNAMIC SCHEDULING FOR EFFICIENT PARA...
- Publication number 20130297279
- Publication date Nov 7, 2013
- Synopsys, Inc.
- Ramesh Narayanaswamy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RETIMING A DESIGN FOR EFFICIENT PARALLEL SIMULATION
- Publication number 20130297278
- Publication date Nov 7, 2013
- Synopsys, Inc.
- Ramesh Narayanaswamy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELECTIVE EXECUTION FOR PARTITIONED PARALLEL SIMULATIONS
- Publication number 20130290919
- Publication date Oct 31, 2013
- Synopsys, Inc.
- Ramesh Narayanaswamy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOGIC SIMULATION AND/OR EMULATION WHICH FOLLOWS HARDWARE SEMANTICS
- Publication number 20100280814
- Publication date Nov 4, 2010
- Synopsys, Inc.
- Alexander Rabinovitch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR DELAY IMMUNE AND ACCELERATED EVALUATION OF DIGITAL CIRCU...
- Publication number 20070294075
- Publication date Dec 20, 2007
- EVE-USA, INC.
- SUBBU GANESAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
A system and method for compiling a description of an electronic ci...
- Publication number 20070044079
- Publication date Feb 22, 2007
- Tharas Systems Inc.
- SUBBU GANESAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
A system and method for simulation of electronic circuits generatin...
- Publication number 20060277428
- Publication date Dec 7, 2006
- Tharas Systems Inc.
- SUBBU GANESAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
A scalable system for simulation and emulation of electronic circui...
- Publication number 20060277019
- Publication date Dec 7, 2006
- THARAS SYSTEMS
- Subbu Ganesan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
A compact processor element for a scalable digital logic verificati...
- Publication number 20060277234
- Publication date Dec 7, 2006
- THARAS SYSTEMS
- Subbu Ganesan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
A reconfigurable system for verification of electronic circuits usi...
- Publication number 20060277020
- Publication date Dec 7, 2006
- THARAS SYSTEMS
- Subbu Ganesan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Functional verification system
- Publication number 20030041308
- Publication date Feb 27, 2003
- Tharas Systems, Inc.
- Subbu Ganesan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Run-time controller in a functional verification system
- Publication number 20020120907
- Publication date Aug 29, 2002
- Tharas Systems, Inc.
- Subbu Ganesan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Tracing different states reached by a signal in a functional verifi...
- Publication number 20020116689
- Publication date Aug 22, 2002
- Subbu Ganesan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Tracing the change of state of a signal in a functional verificatio...
- Publication number 20020116693
- Publication date Aug 22, 2002
- Subbu Ganesan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Functional verification of both cycle-based and non-cycle based des...
- Publication number 20020112217
- Publication date Aug 15, 2002
- Tharas Systems, Inc.
- Subbu Ganesan
- G06 - COMPUTING CALCULATING COUNTING

Ramesh Narayanaswamy

Person

Patents Grantslast 30 patents

Selective execution for partitioned parallel simulations

Logic simulation and/or emulation which follows hardware semantics

Retiming a design for efficient parallel simulation

Quasi-dynamic scheduling and dynamic scheduling for efficient paral...

Method for delay immune and accelerated evaluation of digital circu...

Scalable system for simulation and emulation of electronic circuits...

Compact processor element for a scalable digital logic verification...

Functional verification system

Tracing the change of state of a signal in a functional verificatio...

Run-time controller in a functional verification system

Functional verification of both cycle-based and non-cycle based des...

Tracing different states reached by a signal in a functional verifi...

Patents Applicationslast 30 patents

MESSAGE PASSING MULTI PROCESSOR NETWORK FOR SIMULATION VECTOR PROCE...

CLOCK AWARE SIMULATION VECTOR PROCESSOR

Selective Execution For Partitioned Parallel Simulations

QUASI-DYNAMIC SCHEDULING AND DYNAMIC SCHEDULING FOR EFFICIENT PARA...

RETIMING A DESIGN FOR EFFICIENT PARALLEL SIMULATION

SELECTIVE EXECUTION FOR PARTITIONED PARALLEL SIMULATIONS

LOGIC SIMULATION AND/OR EMULATION WHICH FOLLOWS HARDWARE SEMANTICS

METHOD FOR DELAY IMMUNE AND ACCELERATED EVALUATION OF DIGITAL CIRCU...

A system and method for compiling a description of an electronic ci...

A system and method for simulation of electronic circuits generatin...

A scalable system for simulation and emulation of electronic circui...

A compact processor element for a scalable digital logic verificati...

A reconfigurable system for verification of electronic circuits usi...

Functional verification system

Run-time controller in a functional verification system

Tracing different states reached by a signal in a functional verifi...

Tracing the change of state of a signal in a functional verificatio...

Functional verification of both cycle-based and non-cycle based des...