Ramesh Raghavan

Person

Narsingi, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Wordline system architecture supporting erase operation and I-V cha...
- Patent number 12,176,053
- Issue date Dec 24, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Ramesh Raghavan
- G11 - INFORMATION STORAGE
Information Patent Grant
Sense circuit and high-speed memory structure incorporating the sen...
- Patent number 12,051,465
- Issue date Jul 30, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Chandrahasa Reddy Dinnipati
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and related method to indicate stability and instability...
- Patent number 11,881,258
- Issue date Jan 23, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Ramesh Raghavan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Resistive memory array with localized reference cells
- Patent number 11,881,241
- Issue date Jan 23, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Chandrahasa Reddy Dinnipati
- G11 - INFORMATION STORAGE
Information Patent Grant
Twin cell memory-based physically unclonable function
- Patent number 11,329,836
- Issue date May 10, 2022
- GLOBALFOUNDRIES U.S. Inc.
- Toshiaki Kirihata
- G11 - INFORMATION STORAGE
Information Patent Grant
Data dependent sense amplifier with symmetric margining
- Patent number 11,056,208
- Issue date Jul 6, 2021
- GLOBALFOUNDRIES U.S. INC.
- Balaji Jayaraman
- G11 - INFORMATION STORAGE
Information Patent Grant
Test method and structure for integrated circuits before complete m...
- Patent number 9,859,177
- Issue date Jan 2, 2018
- GLOBALFOUNDRIES Inc.
- Janakiraman Viraraghavan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual-bit 3-T high density MTPROM array
- Patent number 9,786,333
- Issue date Oct 10, 2017
- GLOBALFOUNDRIES Inc.
- Ramesh Raghavan
- G11 - INFORMATION STORAGE
Information Patent Grant
Sense amplifier and latching scheme
- Patent number 9,761,285
- Issue date Sep 12, 2017
- GLOBALFOUNDRIES Inc.
- Venkatraghavan Bringivijayaraghavan
- G11 - INFORMATION STORAGE
Information Patent Grant
Distributed current source/sink using inactive memory elements
- Patent number 9,721,673
- Issue date Aug 1, 2017
- GLOBALFOUNDRIES Inc.
- Ramesh Raghavan
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual-bit 3-T high density MTPROM array
- Patent number 9,659,604
- Issue date May 23, 2017
- GLOBALFOUNDRIES Inc.
- Ramesh Raghavan
- G11 - INFORMATION STORAGE
Information Patent Grant
Disturb free bitcell and array
- Patent number 9,589,658
- Issue date Mar 7, 2017
- GLOBALFOUNDRIES INC.
- Navin Agarwal
- G11 - INFORMATION STORAGE
Information Patent Grant
Data-dependent self-biased differential sense amplifier
- Patent number 9,460,760
- Issue date Oct 4, 2016
- GlobalFoundries Inc.
- Balaji Jayaraman
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
MEMORY ASSEMBLY WITH BODY BIASING AND RELATED METHODS
- Publication number 20240304258
- Publication date Sep 12, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Ramesh Raghavan
- G11 - INFORMATION STORAGE
Information Patent Application
SENSE CIRCUIT AND HIGH-SPEED MEMORY STRUCTURE INCORPORATING THE SEN...
- Publication number 20240021243
- Publication date Jan 18, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Chandrahasa Reddy Dinnipati
- G11 - INFORMATION STORAGE
Information Patent Application
RESISTIVE MEMORY ARRAY WITH LOCALIZED REFERENCE CELLS
- Publication number 20230317130
- Publication date Oct 5, 2023
- GLOBALFOUNDRIES U.S. Inc.
- Chandrahasa Reddy Dinnipati
- G11 - INFORMATION STORAGE
Information Patent Application
WORDLINE SYSTEM ARCHITECTURE SUPPORTING ERASE OPERATION AND I-V CHA...
- Publication number 20230027165
- Publication date Jan 26, 2023
- GLOBALFOUNDRIES U.S. Inc.
- Ramesh RAGHAVAN
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS AND RELATED METHOD TO INDICATE STABILITY AND INSTABILITY...
- Publication number 20230012844
- Publication date Jan 19, 2023
- GLOBALFOUNDRIES U.S. Inc.
- Ramesh Raghavan
- G11 - INFORMATION STORAGE
Information Patent Application
TEST METHOD AND STRUCTURE FOR INTEGRATED CIRCUITS BEFORE COMPLETE M...
- Publication number 20170256468
- Publication date Sep 7, 2017
- GLOBALFOUNDRIES INC.
- Janakiraman Viraraghavan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SENSE AMPLIFIER AND LATCHING SCHEME
- Publication number 20170249976
- Publication date Aug 31, 2017
- GLOBALFOUNDRIES INC.
- Venkatraghavan Bringivijayaraghavan
- G11 - INFORMATION STORAGE
Information Patent Application
DUAL-BIT 3-T HIGH DENSITY MTPROM ARRAY
- Publication number 20170206938
- Publication date Jul 20, 2017
- GLOBALFOUNDRIES INC.
- Ramesh Raghavan
- G11 - INFORMATION STORAGE
Information Patent Application
DUAL-BIT 3-T HIGH DENSITY MTPROM ARRAY
- Publication number 20170162234
- Publication date Jun 8, 2017
- GLOBALFOUNDRIES INC.
- Ramesh Raghavan
- G11 - INFORMATION STORAGE
Information Patent Application
DISTURB FREE BITCELL AND ARRAY
- Publication number 20170053705
- Publication date Feb 23, 2017
- GLOBALFOUNDRIES Inc.
- Navin AGARWAL
- G11 - INFORMATION STORAGE
Information Patent Application
DATA-DEPENDENT SELF-BIASED DIFFERENTIAL SENSE AMPLIFIER
- Publication number 20160217832
- Publication date Jul 28, 2016
- GLOBALFOUNDRIES Inc.
- Balaji Jayaraman
- G11 - INFORMATION STORAGE

Ramesh Raghavan

Person

Patents Grantslast 30 patents

Wordline system architecture supporting erase operation and I-V cha...

Sense circuit and high-speed memory structure incorporating the sen...

Apparatus and related method to indicate stability and instability...

Resistive memory array with localized reference cells

Twin cell memory-based physically unclonable function

Data dependent sense amplifier with symmetric margining

Test method and structure for integrated circuits before complete m...

Dual-bit 3-T high density MTPROM array

Sense amplifier and latching scheme

Distributed current source/sink using inactive memory elements

Dual-bit 3-T high density MTPROM array

Disturb free bitcell and array

Data-dependent self-biased differential sense amplifier

Patents Applicationslast 30 patents

MEMORY ASSEMBLY WITH BODY BIASING AND RELATED METHODS

SENSE CIRCUIT AND HIGH-SPEED MEMORY STRUCTURE INCORPORATING THE SEN...

RESISTIVE MEMORY ARRAY WITH LOCALIZED REFERENCE CELLS

WORDLINE SYSTEM ARCHITECTURE SUPPORTING ERASE OPERATION AND I-V CHA...

APPARATUS AND RELATED METHOD TO INDICATE STABILITY AND INSTABILITY...

TEST METHOD AND STRUCTURE FOR INTEGRATED CIRCUITS BEFORE COMPLETE M...

SENSE AMPLIFIER AND LATCHING SCHEME

DUAL-BIT 3-T HIGH DENSITY MTPROM ARRAY

DUAL-BIT 3-T HIGH DENSITY MTPROM ARRAY

DISTURB FREE BITCELL AND ARRAY

DATA-DEPENDENT SELF-BIASED DIFFERENTIAL SENSE AMPLIFIER