Ramkarthik Ganesan

Person

Folsom, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Data recovery in memory devices
- Patent number 10,303,571
- Issue date May 28, 2019
- Intel Corporation
- Ning Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DDR flash implementation with direct register access to legacy flas...
- Patent number 8,006,029
- Issue date Aug 23, 2011
- Intel Corporation
- Ramkarthik Ganesan
- G11 - INFORMATION STORAGE
Information Patent Grant
DDR flash implementation with hybrid row buffers and direct access...
- Patent number 7,707,378
- Issue date Apr 27, 2010
- Intel Corporation
- Ramkarthik Ganesan
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory adapted to provide dedicated and or shared memory to multipl...
- Patent number 7,380,085
- Issue date May 27, 2008
- Intel Corporation
- Eugene P. Matter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Status register architecture for flexible read-while-write device
- Patent number 6,931,498
- Issue date Aug 16, 2005
- Intel Corporation
- Sanjay S. Talreja
- G11 - INFORMATION STORAGE
Information Patent Grant
Burst suspend and resume with computer memory
- Patent number 6,618,790
- Issue date Sep 9, 2003
- Intel Corporation
- Sanjay S. Talreja
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
STORAGE DEVICE HAVING PROGRAMMED CELL STORAGE DENSITY MODES THAT AR...
- Publication number 20190034105
- Publication date Jan 31, 2019
- Intel Corporation
- Shankar NATARAJAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA RECOVERY IN MEMORY DEVICES
- Publication number 20170123946
- Publication date May 4, 2017
- Intel Corporation
- Ning Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNOLOGIES FOR MANAGING A DYNAMIC READ CACHE OF A SOLID STATE DRIVE
- Publication number 20170075812
- Publication date Mar 16, 2017
- Intel Corporation
- Ning Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DDR FLASH IMPLEMENTATION WITH DIRECT REGISTER ACCESS TO LEGACY FLAS...
- Publication number 20120191898
- Publication date Jul 26, 2012
- Ramkarthik Ganesan
- G11 - INFORMATION STORAGE
Information Patent Application
DDR flash implementation with row buffer interface to legacy flash...
- Publication number 20080133820
- Publication date Jun 5, 2008
- Ramkarthik Ganesan
- G11 - INFORMATION STORAGE
Information Patent Application
DDR flash implementation with hybrid row buffers and direct access...
- Publication number 20080133819
- Publication date Jun 5, 2008
- Ramkarthik Ganesan
- G11 - INFORMATION STORAGE
Information Patent Application
DDR flash implementation with direct register access to legacy flas...
- Publication number 20080133821
- Publication date Jun 5, 2008
- Ramkarthik Ganesan
- G11 - INFORMATION STORAGE
Information Patent Application
Memory adaptedt to provide dedicated and or shared memory to multip...
- Publication number 20030093628
- Publication date May 15, 2003
- Eugene P. Matter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Status register architecture for flexible read-while-write device
- Publication number 20020144066
- Publication date Oct 3, 2002
- Sanjay S. Talreja
- G11 - INFORMATION STORAGE

Ramkarthik Ganesan

Person

Patents Grantslast 30 patents

Data recovery in memory devices

DDR flash implementation with direct register access to legacy flas...

DDR flash implementation with hybrid row buffers and direct access...

Memory adapted to provide dedicated and or shared memory to multipl...

Status register architecture for flexible read-while-write device

Burst suspend and resume with computer memory

Patents Applicationslast 30 patents

STORAGE DEVICE HAVING PROGRAMMED CELL STORAGE DENSITY MODES THAT AR...

DATA RECOVERY IN MEMORY DEVICES

TECHNOLOGIES FOR MANAGING A DYNAMIC READ CACHE OF A SOLID STATE DRIVE

DDR FLASH IMPLEMENTATION WITH DIRECT REGISTER ACCESS TO LEGACY FLAS...

DDR flash implementation with row buffer interface to legacy flash...

DDR flash implementation with hybrid row buffers and direct access...

DDR flash implementation with direct register access to legacy flas...

Memory adaptedt to provide dedicated and or shared memory to multip...

Status register architecture for flexible read-while-write device