Ramon Matas

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Resolving memory accesses crossing cache line boundaries
- Patent number 10,318,427
- Issue date Jun 11, 2019
- Intel Corporation
- Ramon Matas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stateless capture of data linear addresses during precise event bas...
- Patent number 10,175,986
- Issue date Jan 8, 2019
- Intel Corporation
- Roger Gramunt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses, methods, and systems to share translation lookaside bu...
- Patent number 10,108,554
- Issue date Oct 23, 2018
- Intel Corporation
- Chung-Lun Chan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing an efficient scatter
- Patent number 9,891,914
- Issue date Feb 13, 2018
- Intel Corporation
- Ramon Matas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable event handling in multi-threaded processor cores
- Patent number 9,886,396
- Issue date Feb 6, 2018
- Intel Corporation
- Roger Gramunt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory fault suppression via re-execution and hardware FSM
- Patent number 9,715,432
- Issue date Jul 25, 2017
- Intel Corporation
- Ramon Matas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Boot strap processor assignment for a multi-core processing unit
- Patent number 9,658,861
- Issue date May 23, 2017
- Intel Corporation
- Steven S. Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stateless capture of data linear addresses during precise event bas...
- Patent number 9,652,237
- Issue date May 16, 2017
- Intel Corporation
- Roger Gramunt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reset of multi-core processing system
- Patent number 9,389,657
- Issue date Jul 12, 2016
- Intel Corporation
- Steven S. Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Advanced programmable interrupt controller identifier (APIC ID) ass...
- Patent number 9,372,816
- Issue date Jun 21, 2016
- Intel Corporation
- Steven S. Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Initialization of multi-core processing system
- Patent number 9,367,329
- Issue date Jun 14, 2016
- Intel Corporation
- Steven S. Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reset of processing core in multi-core processing system
- Patent number 9,208,124
- Issue date Dec 8, 2015
- Intel Corporation
- Steven S. Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Performing memory accesses using memory context information
- Patent number 8,521,944
- Issue date Aug 27, 2013
- Intel Corporation
- Ramon Matas
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
APPARATUSES, METHODS, AND SYSTEMS TO SHARE TRANSLATION LOOKASIDE BU...
- Publication number 20180157598
- Publication date Jun 7, 2018
- Intel Corporation
- CHUNG-LUN CHAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STATELESS CAPTURE OF DATA LINEAR ADDRESSES DURING PRECISE EVENT BAS...
- Publication number 20170242698
- Publication date Aug 24, 2017
- Intel Corporation
- Roger Gramunt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR PERFORMING AN EFFICIENT SCATTER
- Publication number 20160299762
- Publication date Oct 13, 2016
- RAMON MATAS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY FAULT SUPPRESSION VIA RE-EXECUTION AND HARDWARE FSM
- Publication number 20160179632
- Publication date Jun 23, 2016
- Intel Corporation
- Ramon MATAS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RESOLVING MEMORY ACCESSES CROSSING CACHE LINE BOUNDARIES
- Publication number 20160179677
- Publication date Jun 23, 2016
- RAMON MATAS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALABLE EVENT HANDLING IN MULTI-THREADED PROCESSOR CORES
- Publication number 20160179533
- Publication date Jun 23, 2016
- Roger Gramunt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STATELESS CAPTURE OF DATA LINEAR ADDRESSES DURING PRECISE EVENT BAS...
- Publication number 20160179541
- Publication date Jun 23, 2016
- Roger Gramunt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS TO SHARE MODIFIED DATA WITHOUT WRITE-BACK IN A...
- Publication number 20140189255
- Publication date Jul 3, 2014
- Ramacharan Sundararaman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER IDENTIFIER (APIC ID) ASS...
- Publication number 20140156896
- Publication date Jun 5, 2014
- Steven S. Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INITIALIZATION OF MULTI-CORE PROCESSING SYSTEM
- Publication number 20140006763
- Publication date Jan 2, 2014
- Steven S. Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BOOT STRAP PROCESSOR ASSIGNMENT FOR A MULTI-CORE PROCESSING UNIT
- Publication number 20140006767
- Publication date Jan 2, 2014
- Steven S. Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RESET OF PROCESSING CORE IN MULTI-CORE PROCESSING SYSTEM
- Publication number 20130339663
- Publication date Dec 19, 2013
- Steven S. Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RESET OF MULTI-CORE PROCESSING SYSTEM
- Publication number 20130268747
- Publication date Oct 10, 2013
- Steven S. Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERFORMING MEMORY ACCESSES USING MEMORY CONTEXT INFORMATION
- Publication number 20120054425
- Publication date Mar 1, 2012
- Ramon Matas
- G06 - COMPUTING CALCULATING COUNTING

Ramon Matas

Person

Patents Grantslast 30 patents

Resolving memory accesses crossing cache line boundaries

Stateless capture of data linear addresses during precise event bas...

Apparatuses, methods, and systems to share translation lookaside bu...

Method and apparatus for performing an efficient scatter

Scalable event handling in multi-threaded processor cores

Memory fault suppression via re-execution and hardware FSM

Boot strap processor assignment for a multi-core processing unit

Stateless capture of data linear addresses during precise event bas...

Reset of multi-core processing system

Advanced programmable interrupt controller identifier (APIC ID) ass...

Initialization of multi-core processing system

Reset of processing core in multi-core processing system

Performing memory accesses using memory context information

Patents Applicationslast 30 patents

APPARATUSES, METHODS, AND SYSTEMS TO SHARE TRANSLATION LOOKASIDE BU...

STATELESS CAPTURE OF DATA LINEAR ADDRESSES DURING PRECISE EVENT BAS...

METHOD AND APPARATUS FOR PERFORMING AN EFFICIENT SCATTER

MEMORY FAULT SUPPRESSION VIA RE-EXECUTION AND HARDWARE FSM

RESOLVING MEMORY ACCESSES CROSSING CACHE LINE BOUNDARIES

SCALABLE EVENT HANDLING IN MULTI-THREADED PROCESSOR CORES

STATELESS CAPTURE OF DATA LINEAR ADDRESSES DURING PRECISE EVENT BAS...

METHOD AND APPARATUS TO SHARE MODIFIED DATA WITHOUT WRITE-BACK IN A...

ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER IDENTIFIER (APIC ID) ASS...

INITIALIZATION OF MULTI-CORE PROCESSING SYSTEM

BOOT STRAP PROCESSOR ASSIGNMENT FOR A MULTI-CORE PROCESSING UNIT

RESET OF PROCESSING CORE IN MULTI-CORE PROCESSING SYSTEM

RESET OF MULTI-CORE PROCESSING SYSTEM

PERFORMING MEMORY ACCESSES USING MEMORY CONTEXT INFORMATION