Ramyanshu Datta

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Accelerating test, debug and failure analysis of a multiprocessor d...
- Patent number 7,900,086
- Issue date Mar 1, 2011
- International Business Machines Corporation
- Ramyanshu Datta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shift-and-negate unit within a fused multiply-adder circuit
- Patent number 7,337,202
- Issue date Feb 26, 2008
- International Business Machines Corporation
- Ramyanshu Datta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
4-to-2 carry save adder using limited switching dynamic logic
- Patent number 7,284,029
- Issue date Oct 16, 2007
- International Business Machines Corporation
- Wendy A. Belluomini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Skewed inverter delay line for use in measuring critical paths in a...
- Patent number 7,260,755
- Issue date Aug 21, 2007
- International Business Machines Corporation
- Gary Dale Carpenter
- G01 - MEASURING TESTING
Information Patent Grant
Computing carry-in bit to most significant bit carry save adder in...
- Patent number 7,216,141
- Issue date May 8, 2007
- International Business Machines Corporaiton
- Wendy A. Belluomini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing bit-aligned permute
- Patent number 7,014,122
- Issue date Mar 21, 2006
- International Business Machines Corporation
- Ramyanshu Datta
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Accelerating Test, Debug and Failure Analysis of a Multiprocessor D...
- Publication number 20080229166
- Publication date Sep 18, 2008
- Internaional Business Machines Corporation
- Ramyanshu Datta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR ACCELERATING TEST, DEBUG AND FAILURE ANALY...
- Publication number 20070300115
- Publication date Dec 27, 2007
- Ramyanshu Datta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Skewed inverter delay line for use in measuring critical paths in a...
- Publication number 20060200716
- Publication date Sep 7, 2006
- Gary Dale Carpenter
- G01 - MEASURING TESTING
Information Patent Application
Method and apparatus for performing bit-aligned permute
- Publication number 20050139647
- Publication date Jun 30, 2005
- International Business Machines Corp.
- Ramyanshu Datta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Shift-and-negate unit within a fused multiply-adder circuit
- Publication number 20050144214
- Publication date Jun 30, 2005
- International Business Machines Corporation
- Ramyanshu Datta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Computing carry-in bit to most significant bit carry save adder in...
- Publication number 20050102346
- Publication date May 12, 2005
- International Business Machines Corporation
- Wendy A. Belluomini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
4-to-2 carry save adder using limited switching dynamic logic
- Publication number 20050102345
- Publication date May 12, 2005
- International Business Machines Corporation
- Wendy A. Belluomini
- G06 - COMPUTING CALCULATING COUNTING

Ramyanshu Datta

Person

Patents Grantslast 30 patents

Accelerating test, debug and failure analysis of a multiprocessor d...

Shift-and-negate unit within a fused multiply-adder circuit

4-to-2 carry save adder using limited switching dynamic logic

Skewed inverter delay line for use in measuring critical paths in a...

Computing carry-in bit to most significant bit carry save adder in...

Method and apparatus for performing bit-aligned permute

Patents Applicationslast 30 patents

Accelerating Test, Debug and Failure Analysis of a Multiprocessor D...

APPARATUS AND METHOD FOR ACCELERATING TEST, DEBUG AND FAILURE ANALY...

Skewed inverter delay line for use in measuring critical paths in a...

Method and apparatus for performing bit-aligned permute

Shift-and-negate unit within a fused multiply-adder circuit

Computing carry-in bit to most significant bit carry save adder in...

4-to-2 carry save adder using limited switching dynamic logic