Ran A. Chachick

Person

Providence, RI, US

People

Patents Grantslast 30 patents

Information Patent Grant
Coprocessors with bypass optimization, variable grid architecture,...
- Patent number 12,174,785
- Issue date Dec 24, 2024
- Apple Inc.
- Aditya Kesiraju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coprocessors with bypass optimization, variable grid architecture,...
- Patent number 12,135,681
- Issue date Nov 5, 2024
- Apple Inc.
- Aditya Kesiraju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coprocessor register renaming using registers associated with an in...
- Patent number 11,775,301
- Issue date Oct 3, 2023
- Apple Inc.
- Ran Aharon Chachick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coprocessor context priority
- Patent number 11,768,690
- Issue date Sep 26, 2023
- Apple Inc.
- Aditya Kesiraju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coprocessor synchronizing instruction suppression
- Patent number 11,650,825
- Issue date May 16, 2023
- Apple Inc.
- Aditya Kesiraju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coprocessor synchronizing instruction suppression
- Patent number 11,249,766
- Issue date Feb 15, 2022
- Apple Inc.
- Aditya Kesiraju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coprocessor context priority
- Patent number 11,210,104
- Issue date Dec 28, 2021
- Apple Inc.
- Aditya Kesiraju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coprocessor with distributed register
- Patent number 10,846,091
- Issue date Nov 24, 2020
- Apple Inc.
- Aditya Kesiraju
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Coprocessor Register Renaming
- Publication number 20240045680
- Publication date Feb 8, 2024
- Apple Inc.
- Ran Aharon Chachick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Coprocessor Register Renaming
- Publication number 20230095072
- Publication date Mar 30, 2023
- Apple Inc.
- Ran Aharon Chachick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Coprocessors with Bypass Optimization, Variable Grid Architecture,...
- Publication number 20220358082
- Publication date Nov 10, 2022
- Apple Inc.
- Aditya Kesiraju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Coprocessors with Bypass Optimization, Variable Grid Architecture,...
- Publication number 20220350776
- Publication date Nov 3, 2022
- Apple Inc.
- Aditya Kesiraju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Coprocessor Synchronizing Instruction Suppression
- Publication number 20220214887
- Publication date Jul 7, 2022
- Apple Inc.
- Aditya Kesiraju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Coprocessor Context Priority
- Publication number 20220083343
- Publication date Mar 17, 2022
- Aditya Kesiraju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Coprocessors with Bypass Optimization, Variable Grid Architecture,...
- Publication number 20200272597
- Publication date Aug 27, 2020
- Apple Inc.
- Aditya Kesiraju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Coprocessor with Distributed Register
- Publication number 20200272467
- Publication date Aug 27, 2020
- Apple Inc.
- Aditya Kesiraju
- G06 - COMPUTING CALCULATING COUNTING

Ran A. Chachick

Person

Patents Grantslast 30 patents

Coprocessors with bypass optimization, variable grid architecture,...

Coprocessors with bypass optimization, variable grid architecture,...

Coprocessor register renaming using registers associated with an in...

Coprocessor context priority

Coprocessor synchronizing instruction suppression

Coprocessor synchronizing instruction suppression

Coprocessor context priority

Coprocessor with distributed register

Patents Applicationslast 30 patents

Coprocessor Register Renaming

Coprocessor Register Renaming

Coprocessors with Bypass Optimization, Variable Grid Architecture,...

Coprocessors with Bypass Optimization, Variable Grid Architecture,...

Coprocessor Synchronizing Instruction Suppression

Coprocessor Context Priority

Coprocessors with Bypass Optimization, Variable Grid Architecture,...

Coprocessor with Distributed Register