Ran Ginosar

Person

Nofit, IL

People

Patents Grantslast 30 patents

Information Patent Grant
Resistive address decoder and virtually addressed memory
- Patent number 10,878,906
- Issue date Dec 29, 2020
- Technion Research & Development Foundation Limited
- Leonid Yavits
- G11 - INFORMATION STORAGE
Information Patent Grant
Programming for electronic memories
- Patent number 10,366,752
- Issue date Jul 30, 2019
- Technion Research and Development Foundation Ltd.
- Misbah Ramadan
- G11 - INFORMATION STORAGE
Information Patent Grant
Exploiting the scan test interface for reverse engineering of a VLS...
- Patent number 10,025,896
- Issue date Jul 17, 2018
- Technion Research & Development Foundation Limited
- Leonid Azriel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low power hardware algorithms and architectures for spike sorting a...
- Patent number 9,449,225
- Issue date Sep 20, 2016
- Technion Research & Development Authority
- Ran Ginosar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logic circuit delay optimization
- Patent number 8,225,265
- Issue date Jul 17, 2012
- Technion Research and Development Foundation Ltd.
- Arkadiy Morgenshtein
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated system and method for multichannel neuronal recording wi...
- Patent number 8,090,674
- Issue date Jan 3, 2012
- Technion Research and Development Foundation, Ltd.
- Ran Ginosar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low-power inverted ladder digital-to-analog converter
- Patent number 7,554,475
- Issue date Jun 30, 2009
- Technion Research and Development Foundation Ltd.
- Ran Ginosar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multiple wireless communication protocol methods and apparatuses in...
- Patent number 6,891,857
- Issue date May 10, 2005
- Intel Corporation
- Ron Nevo
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Apparatus and method for parallel processing and self-timed serial...
- Patent number 5,978,899
- Issue date Nov 2, 1999
- Intel Corporation
- Ran Ginosar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for self-timed marking of variable length inst...
- Patent number 5,948,096
- Issue date Sep 7, 1999
- Intel Corporation
- Ran Ginosar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient self-timed marking of lengthy variable length instructions
- Patent number 5,941,982
- Issue date Aug 24, 1999
- Intel Corporation
- Ran Ginosar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Branch instruction handling in a self-timed marking system
- Patent number 5,931,944
- Issue date Aug 3, 1999
- Intel Corporation
- Ran Ginosar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital hardware architecture for realizing neural network
- Patent number 5,812,993
- Issue date Sep 22, 1998
- Technion Research & Development Foundation Ltd.
- Ran Ginosar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus & method for enhancing color images
- Patent number 5,467,123
- Issue date Nov 14, 1995
- Technion Research and Development Foundation, Ltd.
- Yehoshua Y. Zeevi
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Dynamic image representation system
- Patent number 5,420,637
- Issue date May 30, 1995
- i Sight, Inc.
- Yehoshua Y. Zeevi
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Color wide dynamic range camera
- Patent number 5,247,366
- Issue date Sep 21, 1993
- i Sight Ltd.
- Ran Ginosar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
High flow-rate synchronizer/scheduler apparatus and method for mult...
- Patent number 5,202,987
- Issue date Apr 13, 1993
- Nimrod Bayer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Wide dynamic range camera
- Patent number 5,144,442
- Issue date Sep 1, 1992
- i Sight, Inc.
- Ran Ginosar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
RESISTIVE ADDRESS DECODER AND VIRTUALLY ADDRESSED MEMORY
- Publication number 20200051634
- Publication date Feb 13, 2020
- Technion Research & Development Foundation Limited
- Leonid YAVITS
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAMMING FOR ELECTRONIC MEMORIES
- Publication number 20180166137
- Publication date Jun 14, 2018
- Technion Research & Development Foundation Ltd.
- Misbah RAMADAN
- G11 - INFORMATION STORAGE
Information Patent Application
EXPLOITING THE SCAN TEST INTERFACE FOR REVERSE ENGINEERING OF A VLS...
- Publication number 20160328509
- Publication date Nov 10, 2016
- Technion Research & Development Foundation Limited
- Leonid AZRIEL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HYBRID PROCESSOR
- Publication number 20160224465
- Publication date Aug 4, 2016
- Technion Research & Development Foundation Ltd.
- Amir Morad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR SYNCHRONIZING MULTI-CLOCK DOMAINS
- Publication number 20100322365
- Publication date Dec 23, 2010
- TECHNION RESEARCH AND DEVELOPMENT FOUNDATION LTD.
- Rostislav (Reuven) Dobkin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Logic circuit delay optimization
- Publication number 20090150847
- Publication date Jun 11, 2009
- Technion Research & Development Foundation Ltd.
- Arkadiy Morgenshtein
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW POWER HARDWARE ALGORITHMS AND ARCHITECTURES FOR SPIKE SORTING A...
- Publication number 20090124919
- Publication date May 14, 2009
- TECHNION RESEARCH & DEVELPMENT FOUNDATION LTD.
- Ran Ginosar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED SYSTEM AND METHOD FOR MULTICHANNEL NEURONAL RECORDING WI...
- Publication number 20090091377
- Publication date Apr 9, 2009
- Ran Ginosar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Low-Power Inverted Ladder Digital-to-Analog Converter
- Publication number 20080303704
- Publication date Dec 11, 2008
- Ran Ginosar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Clock tuning circuit in chip design
- Publication number 20020073389
- Publication date Jun 13, 2002
- Yaron Elboim
- G06 - COMPUTING CALCULATING COUNTING

Ran Ginosar

Person

Patents Grantslast 30 patents

Resistive address decoder and virtually addressed memory

Programming for electronic memories

Exploiting the scan test interface for reverse engineering of a VLS...

Low power hardware algorithms and architectures for spike sorting a...

Logic circuit delay optimization

Integrated system and method for multichannel neuronal recording wi...

Low-power inverted ladder digital-to-analog converter

Multiple wireless communication protocol methods and apparatuses in...

Apparatus and method for parallel processing and self-timed serial...

Apparatus and method for self-timed marking of variable length inst...

Efficient self-timed marking of lengthy variable length instructions

Branch instruction handling in a self-timed marking system

Digital hardware architecture for realizing neural network

Apparatus & method for enhancing color images

Dynamic image representation system

Color wide dynamic range camera

High flow-rate synchronizer/scheduler apparatus and method for mult...

Wide dynamic range camera

Patents Applicationslast 30 patents

RESISTIVE ADDRESS DECODER AND VIRTUALLY ADDRESSED MEMORY

PROGRAMMING FOR ELECTRONIC MEMORIES

EXPLOITING THE SCAN TEST INTERFACE FOR REVERSE ENGINEERING OF A VLS...

HYBRID PROCESSOR

SYSTEM AND METHOD FOR SYNCHRONIZING MULTI-CLOCK DOMAINS

Logic circuit delay optimization

LOW POWER HARDWARE ALGORITHMS AND ARCHITECTURES FOR SPIKE SORTING A...

INTEGRATED SYSTEM AND METHOD FOR MULTICHANNEL NEURONAL RECORDING WI...

Low-Power Inverted Ladder Digital-to-Analog Converter

Clock tuning circuit in chip design