Ranadeep Dutta

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Austin, TX, US

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Patents Grantslast 30 patents

Information Patent Grant
Methods of forming a P-well in an integrated circuit device
- Patent number 7,273,776
- Issue date Sep 25, 2007
- Legerity, Inc.
- Ranadeep Dutta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bipolar transistor with geometry optimized for device performance,...
- Patent number 7,253,498
- Issue date Aug 7, 2007
- Legerity Inc.
- Ranadeep Dutta
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Methods of forming a P-well in an integrated circuit device
- Publication number 20060024927
- Publication date Feb 2, 2006
- Ranadeep Dutta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Bipolar transistor with geometry optimized for device performance,...
- Publication number 20060006498
- Publication date Jan 12, 2006
- Ranadeep Dutta
- H01 - BASIC ELECTRIC ELEMENTS