Randall Cher Liang Cha

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Singapore, SG

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Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit with self-aligned line and via and manufacturing...
- Patent number 7,119,010
- Issue date Oct 10, 2006
- Chartered Semiconductor Manfacturing Ltd.
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Technique to achieve thick silicide film for ultra-shallow junctions
- Patent number 6,878,623
- Issue date Apr 12, 2005
- Chartered Semiconductor Manufacturing Ltd.
- Cheng Cheh Tan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual silicon-on-insulator device wafer die
- Patent number 6,849,928
- Issue date Feb 1, 2005
- Chartered Semiconductor Manufacturing, Ltd.
- Randall Cher Liang Cha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to produce dual gates (one metal and one poly or metal silic...
- Patent number 6,841,441
- Issue date Jan 11, 2005
- Chartered Semiconductor Manufacturing Ltd.
- Chew Hoe Ang
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Dual silicon-on-insulator device wafer die
- Publication number 20020127816
- Publication date Sep 12, 2002
- Randall Cher Liang Cha
- H01 - BASIC ELECTRIC ELEMENTS