Randy B. Osborne

Person

Cambridge, MA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Memory error detection and correction
- Patent number 12,229,003
- Issue date Feb 18, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Hiroki Noguchi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Direct bonding in microelectronic assemblies
- Patent number 12,057,402
- Issue date Aug 6, 2024
- Intel Corporation
- Aleksandar Aleksov
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bipolar selector with independently tunable threshold voltages
- Patent number 11,792,999
- Issue date Oct 17, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd
- Sheng-Chih Lai
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory error detection and correction
- Patent number 11,762,732
- Issue date Sep 19, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd
- Hiroki Noguchi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bipolar selector with independently tunable threshold voltages
- Patent number 11,404,476
- Issue date Aug 2, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd
- Sheng-Chih Lai
- G11 - INFORMATION STORAGE
Information Patent Grant
Interleaved routing for MRAM cell selection
- Patent number 11,133,044
- Issue date Sep 28, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd
- Katherine Chiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bipolar selector with independently tunable threshold voltages
- Patent number 10,991,756
- Issue date Apr 27, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd
- Sheng-Chih Lai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Random access memory
- Patent number 10,878,872
- Issue date Dec 29, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd
- Randy Osborne
- G11 - INFORMATION STORAGE
Information Patent Grant
Automatic hardware ZLW insertion for IPU image streams
- Patent number 10,580,107
- Issue date Mar 3, 2020
- Intel Corporation
- Mauro Cocco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Concurrent accesses of asymmetrical memory sources
- Patent number 10,558,570
- Issue date Feb 11, 2020
- Intel Corporation
- Nadav Bonen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Operating system transparent system memory abandonment
- Patent number 10,304,418
- Issue date May 28, 2019
- Intel Corporation
- Daniel Greenspan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid memory architectures
- Patent number 10,134,471
- Issue date Nov 20, 2018
- Intel Corporation
- Kumar K. Chinnaswamy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple rank high bandwidth memory
- Patent number 10,079,052
- Issue date Sep 18, 2018
- Intel Corporation
- Christopher P. Mozak
- G11 - INFORMATION STORAGE
Information Patent Grant
Automatic hardware ZLW insertion for IPU image streams
- Patent number 9,983,877
- Issue date May 29, 2018
- Intel Corporation
- Mauro Cocco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple rank high bandwidth memory
- Patent number 9,934,842
- Issue date Apr 3, 2018
- Intel Corporation
- Christopher P. Mozak
- G11 - INFORMATION STORAGE
Information Patent Grant
Interconnection of multiple chips in a package
- Patent number 9,535,865
- Issue date Jan 3, 2017
- Intel Corporation
- Thomas P. Thomas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanisms for clock gating
- Patent number 9,143,120
- Issue date Sep 22, 2015
- Intel Corporation
- Randy B. Osborne
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for selective DRAM precharge
- Patent number 9,087,603
- Issue date Jul 21, 2015
- Intel Corporation
- Randy B. Osborne
- G11 - INFORMATION STORAGE
Information Patent Grant
Scalable schedulers for memory controllers
- Patent number 8,977,811
- Issue date Mar 10, 2015
- Intel Corporation
- Philip Abraham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid memory architectures
- Patent number 8,914,568
- Issue date Dec 16, 2014
- Intel Corporation
- Kumar K. Chinnaswamy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-package input/output clustered interface having full and half-du...
- Patent number 8,902,956
- Issue date Dec 2, 2014
- Intel Corporation
- Thomas P. Thomas
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Memory systems and method for coupling memory chips
- Patent number 8,559,190
- Issue date Oct 15, 2013
- Intel Corporation
- Randy B. Osborne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable schedulers for memory controllers
- Patent number 8,463,987
- Issue date Jun 11, 2013
- Intel Corporation
- Philip Abraham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic random access memory with shadow writes
- Patent number 8,281,101
- Issue date Oct 2, 2012
- Intel Corporation
- Kuljit S. Bains
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory micro-tiling
- Patent number 8,010,754
- Issue date Aug 30, 2011
- Intel Corporation
- James Akiyama
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Memory systems with memory chips down and up
- Patent number 7,990,737
- Issue date Aug 2, 2011
- Intel Corporation
- Randy B. Osborne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory micro-tiling
- Patent number 7,765,366
- Issue date Jul 27, 2010
- Intel Corporation
- James Akiyama
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Chips providing single and consolidated commands
- Patent number 7,752,411
- Issue date Jul 6, 2010
- Intel Corporation
- Randy B. Osborne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory system with both single and consolidated commands
- Patent number 7,673,111
- Issue date Mar 2, 2010
- Intel Corporation
- Shelley Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for selective DRAM precharge
- Patent number 7,519,762
- Issue date Apr 14, 2009
- Intel Corporation
- Randy B. Osborne
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
DIRECT BONDING IN MICROELECTRONIC ASSEMBLIES
- Publication number 20240339410
- Publication date Oct 10, 2024
- Intel Corporation
- Aleksandar Aleksov
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MODULAR MEMORY BLOCKS FOR INTEGRATED CIRCUIT DEVICES
- Publication number 20240222347
- Publication date Jul 4, 2024
- Intel Corporation
- Sagar Suthram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SNOOP FILTER FOR LARGE CACHE USING HASH TECHNIQUE WITH OPTIMAL REFR...
- Publication number 20240202124
- Publication date Jun 20, 2024
- Intel Corporation
- Israel Diamand
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY ERROR DETECTION AND CORRECTION
- Publication number 20240028451
- Publication date Jan 25, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hiroki Noguchi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BIPOLAR SELECTOR WITH INDEPENDENTLY TUNABLE THRESHOLD VOLTAGES
- Publication number 20230363181
- Publication date Nov 9, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Sheng-Chih Lai
- G11 - INFORMATION STORAGE
Information Patent Application
CONFIGURABLE ECC MODE IN DRAM
- Publication number 20230223096
- Publication date Jul 13, 2023
- Intel Corporation
- Kuljit S. BAINS
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CHIP STACK FOR HIGH PERFORMANCE LOGIC CHIPS
- Publication number 20230125041
- Publication date Apr 20, 2023
- Intel Corporation
- Christopher P. MOZAK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FULL DUPLEX DRAM FOR TIGHTLY COUPLED COMPUTE DIE AND MEMORY DIE
- Publication number 20220392519
- Publication date Dec 8, 2022
- Intel Corporation
- Randy B. OSBORNE
- G11 - INFORMATION STORAGE
Information Patent Application
BIPOLAR SELECTOR WITH INDEPENDENTLY TUNABLE THRESHOLD VOLTAGES
- Publication number 20220328560
- Publication date Oct 13, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Sheng-Chih Lai
- G11 - INFORMATION STORAGE
Information Patent Application
THERMAL MANAGEMENT IN HORIZONTALLY OR VERTICALLY STACKED DIES
- Publication number 20220300049
- Publication date Sep 22, 2022
- Intel Corporation
- Somvir Singh Dahiya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY ERROR DETECTION AND CORRECTION
- Publication number 20220114046
- Publication date Apr 14, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hiroki Noguchi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIRECT BONDING IN MICROELECTRONIC ASSEMBLIES
- Publication number 20220093517
- Publication date Mar 24, 2022
- Intel Corporation
- Aleksandar Aleksov
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BIPOLAR SELECTOR WITH INDEPENDENTLY TUNABLE THRESHOLD VOLTAGES
- Publication number 20210233958
- Publication date Jul 29, 2021
- Taiwan Semiconductor Manufacturing Co., LTD
- Sheng-Chih Lai
- G11 - INFORMATION STORAGE
Information Patent Application
DYNAMIC RANGE AND LINEARITY OF RESISTIVE ELEMENTS FOR ANALOG COMPUTING
- Publication number 20200134438
- Publication date Apr 30, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Randy Osborne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RANDOM ACCESS MEMORY
- Publication number 20200135251
- Publication date Apr 30, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Randy OSBORNE
- G11 - INFORMATION STORAGE
Information Patent Application
BIPOLAR SELECTOR WITH INDEPENDENTLY TUNABLE THRESHOLD VOLTAGES
- Publication number 20200127046
- Publication date Apr 23, 2020
- Taiwan Semiconductor Manufacturing Co., LTD
- Sheng-Chih Lai
- G11 - INFORMATION STORAGE
Information Patent Application
INTERLEAVED ROUTING FOR MRAM CELL SELECTION
- Publication number 20190371383
- Publication date Dec 5, 2019
- Taiwan Semiconductor Manufacturing Co., LTD
- Katherine Chiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HYBRID MEMORY ARCHITECTURES
- Publication number 20190172538
- Publication date Jun 6, 2019
- Intel Corporation
- Kumar K. Chinnaswamy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTOMATIC HARDWARE ZLW INSERTION FOR IPU IMAGE STREAMS
- Publication number 20180239605
- Publication date Aug 23, 2018
- Intel Corporation
- Mauro Cocco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE RANK HIGH BANDWIDTH MEMORY
- Publication number 20180226118
- Publication date Aug 9, 2018
- Intel Corporation
- Christopher P. Mozak
- G11 - INFORMATION STORAGE
Information Patent Application
OPERATING SYSTEM TRANSPARENT SYSTEM MEMORY ABANDONMENT
- Publication number 20180089096
- Publication date Mar 29, 2018
- Intel Corporation
- Daniel Greenspan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTOMATIC HARDWARE ZLW INSERTION FOR IPU IMAGE STREAMS
- Publication number 20180088952
- Publication date Mar 29, 2018
- Intel Corporation
- Mauro Cocco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ASYMMETRICAL MEMORY MANAGEMENT
- Publication number 20170300415
- Publication date Oct 19, 2017
- Intel Corporation
- Nadav BONEN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE RANK HIGH BANDWIDTH MEMORY
- Publication number 20170140809
- Publication date May 18, 2017
- Intel Corporation
- Christopher P. Mozak
- G11 - INFORMATION STORAGE
Information Patent Application
HYBRID MEMORY ARCHITECTURES
- Publication number 20150143034
- Publication date May 21, 2015
- Kumar K. Chinnaswamy
- G11 - INFORMATION STORAGE
Information Patent Application
INTERCONNECTION OF MULTIPLE CHIPS IN A PACKAGE UTILIZING ON-PACKAGE...
- Publication number 20140201405
- Publication date Jul 17, 2014
- Thomas P. Thomas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MECHANISMS FOR CLOCK GATING
- Publication number 20140009195
- Publication date Jan 9, 2014
- Randy B. Osborne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ON-PACKAGE INPUT/OUTPUT CLUSTERED INTERFACE HAVING FULL AND HALF-DU...
- Publication number 20130322556
- Publication date Dec 5, 2013
- Thomas P. Thomas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALABLE SCHEDULERS FOR MEMORY CONTROLLERS
- Publication number 20130275664
- Publication date Oct 17, 2013
- Philip Abraham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR SELECTIVE DRAM PRECHARGE
- Publication number 20120294101
- Publication date Nov 22, 2012
- Randy B. Osborne
- G11 - INFORMATION STORAGE

Randy B. Osborne

Person

Patents Grantslast 30 patents

Memory error detection and correction

Direct bonding in microelectronic assemblies

Bipolar selector with independently tunable threshold voltages

Memory error detection and correction

Bipolar selector with independently tunable threshold voltages

Interleaved routing for MRAM cell selection

Bipolar selector with independently tunable threshold voltages

Random access memory

Automatic hardware ZLW insertion for IPU image streams

Concurrent accesses of asymmetrical memory sources

Operating system transparent system memory abandonment

Hybrid memory architectures

Multiple rank high bandwidth memory

Automatic hardware ZLW insertion for IPU image streams

Multiple rank high bandwidth memory

Interconnection of multiple chips in a package

Mechanisms for clock gating

Method and apparatus for selective DRAM precharge

Scalable schedulers for memory controllers

Hybrid memory architectures

On-package input/output clustered interface having full and half-du...

Memory systems and method for coupling memory chips

Scalable schedulers for memory controllers

Dynamic random access memory with shadow writes

Memory micro-tiling

Memory systems with memory chips down and up

Memory micro-tiling

Chips providing single and consolidated commands

Memory system with both single and consolidated commands

Method and apparatus for selective DRAM precharge

Patents Applicationslast 30 patents

DIRECT BONDING IN MICROELECTRONIC ASSEMBLIES

MODULAR MEMORY BLOCKS FOR INTEGRATED CIRCUIT DEVICES

SNOOP FILTER FOR LARGE CACHE USING HASH TECHNIQUE WITH OPTIMAL REFR...

MEMORY ERROR DETECTION AND CORRECTION

BIPOLAR SELECTOR WITH INDEPENDENTLY TUNABLE THRESHOLD VOLTAGES

CONFIGURABLE ECC MODE IN DRAM

MEMORY CHIP STACK FOR HIGH PERFORMANCE LOGIC CHIPS

FULL DUPLEX DRAM FOR TIGHTLY COUPLED COMPUTE DIE AND MEMORY DIE

BIPOLAR SELECTOR WITH INDEPENDENTLY TUNABLE THRESHOLD VOLTAGES

THERMAL MANAGEMENT IN HORIZONTALLY OR VERTICALLY STACKED DIES

MEMORY ERROR DETECTION AND CORRECTION

DIRECT BONDING IN MICROELECTRONIC ASSEMBLIES

BIPOLAR SELECTOR WITH INDEPENDENTLY TUNABLE THRESHOLD VOLTAGES

DYNAMIC RANGE AND LINEARITY OF RESISTIVE ELEMENTS FOR ANALOG COMPUTING

RANDOM ACCESS MEMORY

BIPOLAR SELECTOR WITH INDEPENDENTLY TUNABLE THRESHOLD VOLTAGES

INTERLEAVED ROUTING FOR MRAM CELL SELECTION

HYBRID MEMORY ARCHITECTURES

AUTOMATIC HARDWARE ZLW INSERTION FOR IPU IMAGE STREAMS

MULTIPLE RANK HIGH BANDWIDTH MEMORY

OPERATING SYSTEM TRANSPARENT SYSTEM MEMORY ABANDONMENT

AUTOMATIC HARDWARE ZLW INSERTION FOR IPU IMAGE STREAMS

ASYMMETRICAL MEMORY MANAGEMENT

MULTIPLE RANK HIGH BANDWIDTH MEMORY

HYBRID MEMORY ARCHITECTURES

INTERCONNECTION OF MULTIPLE CHIPS IN A PACKAGE UTILIZING ON-PACKAGE...

MECHANISMS FOR CLOCK GATING

ON-PACKAGE INPUT/OUTPUT CLUSTERED INTERFACE HAVING FULL AND HALF-DU...

SCALABLE SCHEDULERS FOR MEMORY CONTROLLERS

METHOD AND APPARATUS FOR SELECTIVE DRAM PRECHARGE