Randy J. Aksamit

Person

Chandler, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Techniques for forming a compacted array of functional cells
- Patent number 10,217,732
- Issue date Feb 26, 2019
- Intel Corporation
- Rany T. Elsayed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method to reduce memory power consumption by invertin...
- Patent number 9,720,484
- Issue date Aug 1, 2017
- Intel Corporation
- Ming Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory data inversion for reducing power consumption
- Patent number 9,015,507
- Issue date Apr 21, 2015
- Intel Corporation
- Ming Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data inversion based approaches for reducing memory power consumption
- Patent number 8,589,706
- Issue date Nov 19, 2013
- Intel Corporation
- Ming Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low leakage state retention circuit
- Patent number 7,626,434
- Issue date Dec 1, 2009
- Intel Corporation
- Randy J. Aksamit
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Two-latch clocked-LSSD flip-flop
- Patent number 7,492,201
- Issue date Feb 17, 2009
- Marvell International Ltd.
- Randy J. Aksamit
- G01 - MEASURING TESTING
Information Patent Grant
Two-latch clocked-LSSD flip-flop
- Patent number 7,262,648
- Issue date Aug 28, 2007
- Marvell International Ltd.
- Randy J. Aksamit
- G01 - MEASURING TESTING
Information Patent Grant
System and method for data retention with reduced leakage current
- Patent number 7,170,327
- Issue date Jan 30, 2007
- Intel Corporation
- Randy J. Aksamit
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate array architecture
- Patent number 6,480,032
- Issue date Nov 12, 2002
- Intel Corporation
- Randy J. Aksamit
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate array architecture
- Patent number 6,462,583
- Issue date Oct 8, 2002
- Intle Corporation
- Randy J. Aksamit
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
TECHNIQUES FOR FORMING A COMPACTED ARRAY OF FUNCTIONAL CELLS
- Publication number 20170018543
- Publication date Jan 19, 2017
- Intel Corporation
- Rany T. ELSAYED
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DATA INVERSION BASED APPROACHES FOR REDUCING MEMORY POWER CONSUMPTION
- Publication number 20150192977
- Publication date Jul 9, 2015
- Intel Corporation
- Ming ZHANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA INVERSION BASED APPROACHES FOR REDUCING MEMORY POWER CONSUMPTION
- Publication number 20140032827
- Publication date Jan 30, 2014
- Ming Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Low leakage state retention circuit
- Publication number 20080238510
- Publication date Oct 2, 2008
- Randy J. Aksamit
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
TWO-LATCH CLOCKED-LSSD FLIP-FLOP
- Publication number 20070290733
- Publication date Dec 20, 2007
- Randy J. Aksamit
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Two-latch clocked-LSSD flip-flop
- Publication number 20060028259
- Publication date Feb 9, 2006
- Intel Corporation
- Randy J. Aksamit
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
System and method for data retention with reduced leakage current
- Publication number 20040266092
- Publication date Dec 30, 2004
- Intel Corporation
- Randy J. Aksamit
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Gate array architecture
- Publication number 20010045846
- Publication date Nov 29, 2001
- Randy J. Aksamit
- H01 - BASIC ELECTRIC ELEMENTS

Randy J. Aksamit

Person

Patents Grantslast 30 patents

Techniques for forming a compacted array of functional cells

Apparatus and method to reduce memory power consumption by invertin...

Memory data inversion for reducing power consumption

Data inversion based approaches for reducing memory power consumption

Low leakage state retention circuit

Two-latch clocked-LSSD flip-flop

Two-latch clocked-LSSD flip-flop

System and method for data retention with reduced leakage current

Gate array architecture

Gate array architecture

Patents Applicationslast 30 patents

TECHNIQUES FOR FORMING A COMPACTED ARRAY OF FUNCTIONAL CELLS

DATA INVERSION BASED APPROACHES FOR REDUCING MEMORY POWER CONSUMPTION

DATA INVERSION BASED APPROACHES FOR REDUCING MEMORY POWER CONSUMPTION

Low leakage state retention circuit

TWO-LATCH CLOCKED-LSSD FLIP-FLOP

Two-latch clocked-LSSD flip-flop

System and method for data retention with reduced leakage current

Gate array architecture