Ranjan Om

Person

New Delhi, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Processing system, related integrated circuit, device and method
- Patent number 11,822,934
- Issue date Nov 21, 2023
- STMicroelectronics Application GmbH
- Roberto Colombo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Functional safety method, corresponding system-on-chip, device and...
- Patent number 11,436,162
- Issue date Sep 6, 2022
- STMicroelectronics (Grenoble 2) SAS
- Riccardo Gemelli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Redundant storage of error correction code (ECC) checkbits for vali...
- Patent number 11,055,173
- Issue date Jul 6, 2021
- STMicroelectronics (Grenoble 2) SAS
- Om Ranjan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processing system, related integrated circuit, device and method
- Patent number 11,048,525
- Issue date Jun 29, 2021
- STMicroelectronics International N.V.
- Roberto Colombo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory architecture including response manager for error correction...
- Patent number 10,860,415
- Issue date Dec 8, 2020
- STMicroelectronics International N.V.
- Om Ranjan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Redundant storage of error correction code (ECC) checkbits for vali...
- Patent number 10,528,422
- Issue date Jan 7, 2020
- STMicroelectronics International N.V.
- Om Ranjan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory architecture including response manager for error correction...
- Patent number 10,379,937
- Issue date Aug 13, 2019
- STMicroelectronics International N.V.
- Om Ranjan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Electronic device having fault monitoring for a memory and associat...
- Patent number 9,990,245
- Issue date Jun 5, 2018
- STMicroelectronics S.R.L.
- Om Ranjan
- G11 - INFORMATION STORAGE
Information Patent Grant
Safe scheduler for finite state deterministic application
- Patent number 9,558,052
- Issue date Jan 31, 2017
- STMicroelectronics International N.V.
- Om Ranjan
- G05 - CONTROLLING REGULATING
Information Patent Grant
Automatic selection of an on-chip ancillary internal clock generato...
- Patent number 7,038,506
- Issue date May 2, 2006
- STMicroelectronics Pvt. Ltd.
- Ranjan Om
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Processing System, Related Integrated Circuit, Device and Method
- Publication number 20210294534
- Publication date Sep 23, 2021
- STMicroelectronics Application GMBH
- Roberto Colombo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FUNCTIONAL SAFETY METHOD, CORRESPONDING SYSTEM-ON-CHIP, DEVICE AND...
- Publication number 20200379924
- Publication date Dec 3, 2020
- STMicroelectronics (Grenoble 2) SAS
- Riccardo Gemelli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUNDANT STORAGE OF ERROR CORRECTION CODE (ECC) CHECKBITS FOR VALI...
- Publication number 20200110663
- Publication date Apr 9, 2020
- STMicroelectronics (Grenoble 2) SAS
- Om RANJAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY ARCHITECTURE INCLUDING RESPONSE MANAGER FOR ERROR CORRECTION...
- Publication number 20190317851
- Publication date Oct 17, 2019
- STMicroelectronics International N.V.
- Om RANJAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSING SYSTEM, RELATED INTEGRATED CIRCUIT, DEVICE AND METHOD
- Publication number 20190258493
- Publication date Aug 22, 2019
- STMicroelectronics Application GMBH
- Roberto Colombo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUNDANT STORAGE OF ERROR CORRECTION CODE (ECC) CHECKBITS FOR VALI...
- Publication number 20190146868
- Publication date May 16, 2019
- STMicroelectronics International N.V.
- Om Ranjan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY ARCHITECTURE INCLUDING RESPONSE MANAGER FOR ERROR CORRECTION...
- Publication number 20190129790
- Publication date May 2, 2019
- STMicroelectronics International N.V.
- Om Ranjan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ELECTRONIC DEVICE HAVING FAULT MONITORING FOR A MEMORY AND ASSOCIAT...
- Publication number 20170147416
- Publication date May 25, 2017
- STMicroelectronics International N.V
- Om RANJAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SAFE SCHEDULER FOR FINITE STATE DETERMINISTIC APPLICATION
- Publication number 20150268133
- Publication date Sep 24, 2015
- STMicroelectronics S.r.l.
- Om Ranjan
- G01 - MEASURING TESTING
Information Patent Application
Automatic selection of an on-chip ancillary internal clock generato...
- Publication number 20050212571
- Publication date Sep 29, 2005
- STMicroelectronics Pvt. Ltd.
- Ranjan Om
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Processing system, related integrated circuit, device and method

Functional safety method, corresponding system-on-chip, device and...

Redundant storage of error correction code (ECC) checkbits for vali...

Processing system, related integrated circuit, device and method

Memory architecture including response manager for error correction...

Redundant storage of error correction code (ECC) checkbits for vali...

Memory architecture including response manager for error correction...

Electronic device having fault monitoring for a memory and associat...

Safe scheduler for finite state deterministic application

Automatic selection of an on-chip ancillary internal clock generato...

Patents Applicationslast 30 patents

Processing System, Related Integrated Circuit, Device and Method

FUNCTIONAL SAFETY METHOD, CORRESPONDING SYSTEM-ON-CHIP, DEVICE AND...

REDUNDANT STORAGE OF ERROR CORRECTION CODE (ECC) CHECKBITS FOR VALI...

MEMORY ARCHITECTURE INCLUDING RESPONSE MANAGER FOR ERROR CORRECTION...

PROCESSING SYSTEM, RELATED INTEGRATED CIRCUIT, DEVICE AND METHOD

REDUNDANT STORAGE OF ERROR CORRECTION CODE (ECC) CHECKBITS FOR VALI...

MEMORY ARCHITECTURE INCLUDING RESPONSE MANAGER FOR ERROR CORRECTION...

ELECTRONIC DEVICE HAVING FAULT MONITORING FOR A MEMORY AND ASSOCIAT...

SAFE SCHEDULER FOR FINITE STATE DETERMINISTIC APPLICATION

Automatic selection of an on-chip ancillary internal clock generato...