Rao H. Desineni

Person

Essex Junction, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Insertion of faults in logic model used in simulation
- Patent number 8,566,059
- Issue date Oct 22, 2013
- International Business Machines Corporation
- Rao H. Desineni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for testing integrated circuits
- Patent number 8,136,082
- Issue date Mar 13, 2012
- International Business Machines Corporation
- Rao H. Desineni
- G01 - MEASURING TESTING
Information Patent Grant
Method for testing integrated circuits
- Patent number 7,971,176
- Issue date Jun 28, 2011
- International Business Machines Corporation
- Rao H. Desineni
- G01 - MEASURING TESTING
Information Patent Grant
Method for determining features associated with fails of integrated...
- Patent number 7,870,519
- Issue date Jan 11, 2011
- International Business Machines Corporation
- Rao H. Desineni
- G01 - MEASURING TESTING
Information Patent Grant
System and method for signature-based systematic condition detectio...
- Patent number 7,853,848
- Issue date Dec 14, 2010
- International Business Machines Corporation
- Rao H. Desineni
- G01 - MEASURING TESTING
Information Patent Grant
Using neighborhood functions to extract logical models of physical...
- Patent number 7,770,080
- Issue date Aug 3, 2010
- Carnegie Mellon University
- Ronald DeShawn Blanton
- G01 - MEASURING TESTING
Information Patent Grant
Method of adaptively selecting chips for reducing in-line testing i...
- Patent number 7,682,842
- Issue date Mar 23, 2010
- International Business Machines Corporation
- Rao H. Desineni
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
INSERTION OF FAULTS IN LOGIC MODEL USED IN SIMULATION
- Publication number 20110137602
- Publication date Jun 9, 2011
- International Business Machines Corporation
- Rao H. Desineni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of Adaptively Selecting Chips for Reducing In-line Testing i...
- Publication number 20090299679
- Publication date Dec 3, 2009
- International Business Machines Corporation
- RAO H. DESINENI
- G01 - MEASURING TESTING
Information Patent Application
METHOD FOR TESTING INTEGRATED CIRCUITS
- Publication number 20090240458
- Publication date Sep 24, 2009
- Rao H. Desineni
- G01 - MEASURING TESTING
Information Patent Application
METHOD FOR TESTING AN INTEGRATED CIRCUIT AND ANALYZING TEST DATA
- Publication number 20090132976
- Publication date May 21, 2009
- Rao H. Desineni
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM AND METHOD FOR SIGNATURE-BASED SYSTEMATIC CONDITION DETECTIO...
- Publication number 20090106614
- Publication date Apr 23, 2009
- Rao H. Desineni
- G01 - MEASURING TESTING
Information Patent Application
Using neighborhood functions to extract logical models of physical...
- Publication number 20070234161
- Publication date Oct 4, 2007
- Ronald DeShawn Blanton
- G01 - MEASURING TESTING

Rao H. Desineni

Person

Patents Grantslast 30 patents

Insertion of faults in logic model used in simulation

Method for testing integrated circuits

Method for testing integrated circuits

Method for determining features associated with fails of integrated...

System and method for signature-based systematic condition detectio...

Using neighborhood functions to extract logical models of physical...

Method of adaptively selecting chips for reducing in-line testing i...

Patents Applicationslast 30 patents

INSERTION OF FAULTS IN LOGIC MODEL USED IN SIMULATION

Method of Adaptively Selecting Chips for Reducing In-line Testing i...

METHOD FOR TESTING INTEGRATED CIRCUITS

METHOD FOR TESTING AN INTEGRATED CIRCUIT AND ANALYZING TEST DATA

SYSTEM AND METHOD FOR SIGNATURE-BASED SYSTEMATIC CONDITION DETECTIO...

Using neighborhood functions to extract logical models of physical...