Raul A. Garibay Jr.

Person

Richardson, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
METHOD FOR CONTROLLING POWER OF A MICROPROCESSOR BY ASSERTING AND D...
- Patent number 6,721,894
- Issue date Apr 13, 2004
- National Semiconductor Corporation
- Robert Maher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
SYSTEM FOR CONTROLLING POWER OF A MICROPROCESSOR BY ASSERTING AND D...
- Patent number 6,694,443
- Issue date Feb 17, 2004
- National Semiconductor Corporation
- Robert Maher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of invoking a low power mode in a computer system using a ha...
- Patent number 6,343,363
- Issue date Jan 29, 2002
- National Semiconductor Corporation
- Robert Maher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method of retiring misaligned write operands from a writ...
- Patent number 6,219,773
- Issue date Apr 17, 2001
- VIA-Cyrix, Inc.
- Raul A. Garibay
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor with multiple execution pipelines using pipe stage state...
- Patent number 6,138,230
- Issue date Oct 24, 2000
- VIA-Cyrix, Inc.
- Mark W. Hervin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer system with low power mode invoked by halt instruction
- Patent number 6,088,807
- Issue date Jul 11, 2000
- National Semiconductor Corporation
- Robert Maher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Address translation unit employing programmable page size
- Patent number 5,963,984
- Issue date Oct 5, 1999
- National Semiconductor Corporation
- Raul A. Garibay
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method of retiring store data from a write buffer
- Patent number 5,907,860
- Issue date May 25, 1999
- National Semiconductor Corporation
- Raul A. Garibay
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coherency for write-back cache in a system designed for write-throu...
- Patent number 5,860,111
- Issue date Jan 12, 1999
- National Semiconductor Corporation
- Marvin Wayne Martinez
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of identifying and self-modifying code
- Patent number 5,835,949
- Issue date Nov 10, 1998
- National Semiconductor Corporation
- Marc A. Quattromani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
In a pipelined processor, setting a segment access indicator during...
- Patent number 5,805,879
- Issue date Sep 8, 1998
- Cyrix Corporation
- Mark W. Hervin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Address translation unit employing a victim TLB
- Patent number 5,752,274
- Issue date May 12, 1998
- Cyrix Corporation
- Raul A. Garibay
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coherency for write-back cache in a system designed for write-throu...
- Patent number 5,664,149
- Issue date Sep 2, 1997
- Cyrix Corporation
- Marvin Wayne Martinez
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor with single clock decode architecture employing single mi...
- Patent number 5,644,741
- Issue date Jul 1, 1997
- Cyrix Corporation
- Mark W. Bluhm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microprocessor having power management circuitry with coprocessor s...
- Patent number 5,632,037
- Issue date May 20, 1997
- Cyrix Corporation
- Robert Maher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microprocessor with externally controllable power management
- Patent number 5,630,143
- Issue date May 13, 1997
- Cyrix Corporation
- Robert Maher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Unified write buffer having information identifying whether the add...
- Patent number 5,615,402
- Issue date Mar 25, 1997
- Cyrix Corporation
- Marc A. Quattromani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit and method for addressing segment descriptor tables
- Patent number 5,596,735
- Issue date Jan 21, 1997
- Cyrix Corporation
- Mark W. Hervin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method of retiring store data from a write buffer
- Patent number 5,584,009
- Issue date Dec 10, 1996
- Cyrix Corporation
- Raul A. Garibay
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Control logic for a sequential data buffer using byte read-enable l...
- Patent number 5,572,682
- Issue date Nov 5, 1996
- Cyrix Corporation
- Raul A. Garibay
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coherency for write-back cache in a system designed for write-throu...
- Patent number 5,524,234
- Issue date Jun 4, 1996
- Cyrix Corporation
- Marvin W. Martinez
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Exception handling for prefetched instruction bytes using valid bit...
- Patent number 5,479,616
- Issue date Dec 26, 1995
- Cyrix Corporation
- Raul A. Garibay
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data dependency detection and handling in a microprocessor with wri...
- Patent number 5,471,598
- Issue date Nov 28, 1995
- Cyrix Corporation
- Marc A. Quattromani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microprocessor for selectively configuring pinout by activating tri...
- Patent number 5,375,209
- Issue date Dec 20, 1994
- Cyrix Corporation
- Robert Maher
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Power management method for a pipelined computer system
- Publication number 20080109667
- Publication date May 8, 2008
- National Semiconductor Corporation
- Robert Maher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Pipelined computer system with power management control
- Publication number 20080098248
- Publication date Apr 24, 2008
- National Semiconductor Corporation
- Robert Maher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Instruction-initiated method for suspending operation of a pipeline...
- Publication number 20050036261
- Publication date Feb 17, 2005
- Robert Maher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Instruction-initiated power management method for a pipelined data...
- Publication number 20050024802
- Publication date Feb 3, 2005
- Robert Maher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Pipelined data processor with instruction-initiated power managemen...
- Publication number 20040230852
- Publication date Nov 18, 2004
- Robert Maher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Signal-initiated power management method for a pipelined data proce...
- Publication number 20040172567
- Publication date Sep 2, 2004
- Robert Maher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Signal-initiated method for suspending operation of a pipelined dat...
- Publication number 20040172568
- Publication date Sep 2, 2004
- Robert Maher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Pipelined data processor with signal-initiated power management con...
- Publication number 20040172572
- Publication date Sep 2, 2004
- Robert Maher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Microprocessor power management control method
- Publication number 20030084355
- Publication date May 1, 2003
- Robert Maheb
- G06 - COMPUTING CALCULATING COUNTING

Raul A. Garibay Jr.

Person

Patents Grantslast 30 patents

METHOD FOR CONTROLLING POWER OF A MICROPROCESSOR BY ASSERTING AND D...

SYSTEM FOR CONTROLLING POWER OF A MICROPROCESSOR BY ASSERTING AND D...

Method of invoking a low power mode in a computer system using a ha...

System and method of retiring misaligned write operands from a writ...

Processor with multiple execution pipelines using pipe stage state...

Computer system with low power mode invoked by halt instruction

Address translation unit employing programmable page size

System and method of retiring store data from a write buffer

Coherency for write-back cache in a system designed for write-throu...

Method of identifying and self-modifying code

In a pipelined processor, setting a segment access indicator during...

Address translation unit employing a victim TLB

Coherency for write-back cache in a system designed for write-throu...

Processor with single clock decode architecture employing single mi...

Microprocessor having power management circuitry with coprocessor s...

Microprocessor with externally controllable power management

Unified write buffer having information identifying whether the add...

Circuit and method for addressing segment descriptor tables

System and method of retiring store data from a write buffer

Control logic for a sequential data buffer using byte read-enable l...

Coherency for write-back cache in a system designed for write-throu...

Exception handling for prefetched instruction bytes using valid bit...

Data dependency detection and handling in a microprocessor with wri...

Microprocessor for selectively configuring pinout by activating tri...

Patents Applicationslast 30 patents

Power management method for a pipelined computer system

Pipelined computer system with power management control

Instruction-initiated method for suspending operation of a pipeline...

Instruction-initiated power management method for a pipelined data...

Pipelined data processor with instruction-initiated power managemen...

Signal-initiated power management method for a pipelined data proce...

Signal-initiated method for suspending operation of a pipelined dat...

Pipelined data processor with signal-initiated power management con...

Microprocessor power management control method