Ravi Kolagotla

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Versatile protected input/output device access and isolated servici...
- Patent number 9,846,592
- Issue date Dec 19, 2017
- Intel Corporation
- Nitin V. Sarangdhar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, apparatus, system for representing, specifying and using de...
- Patent number 9,563,579
- Issue date Feb 7, 2017
- Intel Corporation
- Daniel F. Cutter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Accessing data from different memory locations in the same cycle
- Patent number 7,533,232
- Issue date May 12, 2009
- Intel Corporation
- Ramesh V. Peri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable traceback technique for channel decoder
- Patent number 7,506,239
- Issue date Mar 17, 2009
- Raghavan Sudhakar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Virtualized load buffers
- Patent number 7,346,735
- Issue date Mar 18, 2008
- Intel Corporation
- Ramesh Peri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for extending the local memory address space of a processor
- Patent number 7,174,429
- Issue date Feb 6, 2007
- Intel Corporation
- Juan G. Revilla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data synchronization for a test access port
- Patent number 7,168,032
- Issue date Jan 23, 2007
- Intel Corporation
- Charles P. Roth
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
General purpose register file architecture for aligned simd
- Patent number 7,120,781
- Issue date Oct 10, 2006
- Intel Corporation
- Ravi Kolagotla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Single-step processing and selecting debugging modes
- Patent number 6,986,026
- Issue date Jan 10, 2006
- Intel Corporation
- Charles P. Roth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Maintaining even and odd array pointers to extreme values by search...
- Patent number 6,948,056
- Issue date Sep 20, 2005
- Intel Corporation
- Charles P. Roth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DSP unit for multi-level global accumulation
- Patent number 6,820,102
- Issue date Nov 16, 2004
- Intel Corporation
- Bradley C. Aldrich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor reset and instruction fetches
- Patent number 6,789,187
- Issue date Sep 7, 2004
- Intel Corporation
- Ravi P. Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modulo addressing
- Patent number 6,760,830
- Issue date Jul 6, 2004
- Intel Corporation
- Ryo Inoue
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Event vector table override
- Patent number 6,760,800
- Issue date Jul 6, 2004
- Intel Corporation
- Charles P. Roth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DSP unit for multi-level global accumulation
- Patent number 6,601,077
- Issue date Jul 29, 2003
- Intel Corporation
- Bradley C. Aldrich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System having a configurable cache/SRAM memory
- Patent number 6,446,181
- Issue date Sep 3, 2002
- Intel Corporation
- Hebbalalu S. Ramagopal
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
VERSATILE INPUT/OUTPUT DEVICE ACCESS FOR VIRTUAL MACHINES
- Publication number 20170185434
- Publication date Jun 29, 2017
- Nitin V. Sarangdhar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method, Apparatus, System For Representing, Specifying And Using De...
- Publication number 20140240326
- Publication date Aug 28, 2014
- Daniel F. Cutter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IMAGE SIGNAL PROCESSOR ARCHITECTURE OPTIMIZED FOR LOW-POWER, PROCES...
- Publication number 20130004071
- Publication date Jan 3, 2013
- YUH-LIN E. CHANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus to save and restore context using scan cells
- Publication number 20070136564
- Publication date Jun 14, 2007
- Intel Corporation
- Sankaran Menon
- G11 - INFORMATION STORAGE
Information Patent Application
VIRTUALIZED LOAD BUFFERS
- Publication number 20070112998
- Publication date May 17, 2007
- Ramesh Peri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scalable traceback technique for channel decoder
- Publication number 20060143554
- Publication date Jun 29, 2006
- Raghavan Sudhakar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Maintaining even and odd array pointers to extreme values by search...
- Publication number 20060101230
- Publication date May 11, 2006
- Charles P. Roth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Virtualized load buffers
- Publication number 20050228951
- Publication date Oct 13, 2005
- Ramesh Peri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus to compact trace in a trace buffer
- Publication number 20050223364
- Publication date Oct 6, 2005
- Ramesh V. Peri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Branch prediction in a pipelined processor
- Publication number 20050223202
- Publication date Oct 6, 2005
- Intel Corporation
- Ramesh V. Peri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Accessing data from different memory locations in the same cycle
- Publication number 20050108493
- Publication date May 19, 2005
- Ramesh V. Peri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DSP unit for multi-level global accumulation
- Publication number 20040071041
- Publication date Apr 15, 2004
- Intel Corporation, a Delaware corporation
- Bradley C. Aldrich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Single-step processing and selecting debugging modes
- Publication number 20040073780
- Publication date Apr 15, 2004
- Charles P. Roth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for extending the local memory address space of a processor
- Publication number 20030126367
- Publication date Jul 3, 2003
- Juan G. Revilla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Modulo addressing
- Publication number 20020124039
- Publication date Sep 5, 2002
- Ryo Inoue
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Data synchronization for a test access port
- Publication number 20020078420
- Publication date Jun 20, 2002
- Charles P. Roth
- G01 - MEASURING TESTING
Information Patent Application
Extended processor reset
- Publication number 20020078336
- Publication date Jun 20, 2002
- Intel Corporation and Analog Devices, Inc.
- Ravi P. Singh
- G06 - COMPUTING CALCULATING COUNTING

Ravi Kolagotla

Person

Patents Grantslast 30 patents

Versatile protected input/output device access and isolated servici...

Method, apparatus, system for representing, specifying and using de...

Accessing data from different memory locations in the same cycle

Scalable traceback technique for channel decoder

Virtualized load buffers

Method for extending the local memory address space of a processor

Data synchronization for a test access port

General purpose register file architecture for aligned simd

Single-step processing and selecting debugging modes

Maintaining even and odd array pointers to extreme values by search...

DSP unit for multi-level global accumulation

Processor reset and instruction fetches

Modulo addressing

Event vector table override

DSP unit for multi-level global accumulation

System having a configurable cache/SRAM memory

Patents Applicationslast 30 patents

VERSATILE INPUT/OUTPUT DEVICE ACCESS FOR VIRTUAL MACHINES

Method, Apparatus, System For Representing, Specifying And Using De...

IMAGE SIGNAL PROCESSOR ARCHITECTURE OPTIMIZED FOR LOW-POWER, PROCES...

Method and apparatus to save and restore context using scan cells

VIRTUALIZED LOAD BUFFERS

Scalable traceback technique for channel decoder

Maintaining even and odd array pointers to extreme values by search...

Virtualized load buffers

Method and apparatus to compact trace in a trace buffer

Branch prediction in a pipelined processor

Accessing data from different memory locations in the same cycle

DSP unit for multi-level global accumulation

Single-step processing and selecting debugging modes

Method for extending the local memory address space of a processor

Modulo addressing

Data synchronization for a test access port

Extended processor reset