Ravi Kumar Singh

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Using a hardware sequencer in a direct memory access system of a sy...
- Patent number 12,204,475
- Issue date Jan 21, 2025
- NVIDIA Corporation
- Ahmad Itani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Performing load and permute with a single instruction in a system o...
- Patent number 12,118,353
- Issue date Oct 15, 2024
- NVIDIA Corporation
- Ching-Yu Hung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Performing load and store operations of 2D arrays in a single cycle...
- Patent number 12,099,439
- Issue date Sep 24, 2024
- NVIDIA Corporation
- Ching-Yu Hung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using per memory bank load caches for reducing power use in a syste...
- Patent number 12,093,539
- Issue date Sep 17, 2024
- NVIDIA Corporation
- Ching-Yu Hung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Built-in self-test for a programmable vision accelerator of a syste...
- Patent number 12,050,548
- Issue date Jul 30, 2024
- NVIDIA Corporation
- Ahmad Itani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reduced memory write requirements in a system on a chip using autom...
- Patent number 11,954,496
- Issue date Apr 9, 2024
- NVIDIA Corporation
- Ching-Yu Hung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware accelerated anomaly detection using a min/max collector in...
- Patent number 11,940,947
- Issue date Mar 26, 2024
- NVIDIA Corporation
- Ching-Yu Hung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using a vector processor to configure a direct memory access system...
- Patent number 11,934,829
- Issue date Mar 19, 2024
- NVIDIA Corporation
- Ahmad Itani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Accelerating table lookups using a decoupled lookup table accelerat...
- Patent number 11,836,527
- Issue date Dec 5, 2023
- NVIDIA Corporation
- Ravi P Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Performing multiple point table lookups in a single cycle in a syst...
- Patent number 11,704,067
- Issue date Jul 18, 2023
- NVIDIA Corporation
- Ching-Yu Hung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware accelerated anomaly detection using a min/max collector in...
- Patent number 11,636,063
- Issue date Apr 25, 2023
- NVIDIA Corporation
- Ching-Yu Hung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable vision accelerator
- Patent number 11,630,800
- Issue date Apr 18, 2023
- NVIDIA Corporation
- Ching Y. Hung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using a hardware sequencer in a direct memory access system of a sy...
- Patent number 11,593,290
- Issue date Feb 28, 2023
- NVIDIA Corporation
- Ahmad Itani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using per memory bank load caches for reducing power use in a syste...
- Patent number 11,593,001
- Issue date Feb 28, 2023
- NVIDIA Corporation
- Ching-Yu Hung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using a vector processor to configure a direct memory access system...
- Patent number 11,573,795
- Issue date Feb 7, 2023
- NVIDIA Corporation
- Ahmad Itani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Built-in self-test for a programmable vision accelerator of a syste...
- Patent number 11,573,921
- Issue date Feb 7, 2023
- NVIDIA Corporation
- Ahmad Itani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Middleware for multiprocessor software testing
- Patent number 8,850,267
- Issue date Sep 30, 2014
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Manish K. Aggarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive encoding and decoding for error protected packet-based frames
- Patent number 8,671,333
- Issue date Mar 11, 2014
- LSI Corporation
- Ravi Kumar Singh
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multi-cycle instructions
- Patent number 7,472,259
- Issue date Dec 30, 2008
- Analog Devices, Inc.
- Gregory A. Overkamp
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient emulation instruction dispatch based on instruction width
- Patent number 7,366,876
- Issue date Apr 29, 2008
- Analog Devices, Inc.
- Charles P. Roth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Variable width alignment engine for aligning instructions based on...
- Patent number 7,360,059
- Issue date Apr 15, 2008
- Analog Devices, Inc.
- Thomas Tomazin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Early exception detection
- Patent number 7,272,705
- Issue date Sep 18, 2007
- Analog Devices, Inc.
- Juan G. Revilla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for branch prediction based on branch targets...
- Patent number 7,266,676
- Issue date Sep 4, 2007
- Analog Devices, Inc.
- Thang M. Tran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data synchronization for a test access port
- Patent number 7,168,032
- Issue date Jan 23, 2007
- Intel Corporation
- Charles P. Roth
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
FIFO write/LIFO read trace buffer with software and hardware loop c...
- Patent number 7,155,570
- Issue date Dec 26, 2006
- Intel Corporation
- Ravi P. Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for instruction alignment including current i...
- Patent number 7,134,000
- Issue date Nov 7, 2006
- Analog Devices, Inc.
- Thang M. Tran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Aligning instructions using a variable width alignment engine havin...
- Patent number 7,082,516
- Issue date Jul 25, 2006
- Intel Corporation
- Thomas Tomazin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Decode and dispatch of multi-issue and multiple width instructions
- Patent number 7,069,420
- Issue date Jun 27, 2006
- Intel Corporation
- Gregory A. Overkamp
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware loops and pipeline system using advanced generation of loo...
- Patent number 7,065,636
- Issue date Jun 20, 2006
- Intel Corporation
- Ryo Inoue
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Self-nesting interrupts
- Patent number 7,043,582
- Issue date May 9, 2006
- Intel Corporation
- Ravi P. Singh
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
USING A HARDWARE SEQUENCER IN A DIRECT MEMORY ACCESS SYSTEM OF A SY...
- Publication number 20250103529
- Publication date Mar 27, 2025
- NVIDIA Corporation
- Ahmad Itani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USING A VECTOR PROCESSOR TO CONFIGURE A DIRECT MEMORY ACCESS SYSTEM...
- Publication number 20240134645
- Publication date Apr 25, 2024
- NVIDIA Corporation
- Ahmad Itani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCELERATING TABLE LOOKUPS USING A DECOUPLED LOOKUP TABLE ACCELERAT...
- Publication number 20240045722
- Publication date Feb 8, 2024
- NVIDIA Corporation
- Ravi P. Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USING A VECTOR PROCESSOR TO CONFIGURE A DIRECT MEMORY ACCESS SYSTEM...
- Publication number 20230185569
- Publication date Jun 15, 2023
- NVIDIA Corporation
- Ahmad Itani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE ACCELERATED ANOMALY DETECTION IN A SYSTEM ON A CHIP
- Publication number 20230153266
- Publication date May 18, 2023
- NVIDIA Corpration
- Ching-Yu Hung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HYBRID SOLUTION FOR STEREO IMAGING
- Publication number 20230130478
- Publication date Apr 27, 2023
- NVIDIA Corporation
- Dong Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BUILT-IN SELF-TEST FOR A PROGRAMMABLE VISION ACCELERATOR OF A SYSTE...
- Publication number 20230125397
- Publication date Apr 27, 2023
- NVIDIA Corporation
- Ahmad Itani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USING PER MEMORY BANK LOAD CACHES FOR REDUCING POWER USE IN A SYSTE...
- Publication number 20230124604
- Publication date Apr 20, 2023
- NVIDIA Corporation
- Ching-Yu Hung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USING A HARDWARE SEQUENCER IN A DIRECT MEMORY ACCESS SYSTEM OF A SY...
- Publication number 20230111014
- Publication date Apr 13, 2023
- NVIDIA Corporation
- Ahmad Itani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERFORMING LOAD AND PERMUTE WITH A SINGLE INSTRUCTION IN A SYSTEM O...
- Publication number 20230076599
- Publication date Mar 9, 2023
- NVIDIA Corporation
- Ching-Yu Hung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USING A VECTOR PROCESSOR TO CONFIGURE A DIRECT MEMORY ACCESS SYSTEM...
- Publication number 20230048836
- Publication date Feb 16, 2023
- NVIDIA Corporation
- Ahmad Itani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIMD DATA PATH ORGANIZATION TO INCREASE PROCESSING THROUGHPUT IN A...
- Publication number 20230050062
- Publication date Feb 16, 2023
- NVIDIA Corporation
- Ching-Yu Hung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCELERATING TABLE LOOKUPS USING A DECOUPLED LOOKUP TABLE ACCELERAT...
- Publication number 20230050902
- Publication date Feb 16, 2023
- NVIDIA Corporation
- Ravi P. Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERFORMING MULTIPLE POINT TABLE LOOKUPS IN A SINGLE CYCLE IN A SYST...
- Publication number 20230053042
- Publication date Feb 16, 2023
- NVIDIA Corporation
- Ching-Yu Hung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE ACCELERATED ANOMALY DETECTION IN A SYSTEM ON A CHIP
- Publication number 20230046642
- Publication date Feb 16, 2023
- NVIDIA Corporation
- Ching-Yu Hung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USING PER MEMORY BANK LOAD CACHES FOR REDUCING POWER USE IN A SYSTE...
- Publication number 20230047233
- Publication date Feb 16, 2023
- NVIDIA Corporation
- Ching-Yu Hung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCED MEMORY WRITE REQUIREMENTS IN A SYSTEM ON A CHIP USING AUTOM...
- Publication number 20230049442
- Publication date Feb 16, 2023
- NVIDIA Corporation
- Ching-Yu Hung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERFORMING LOAD AND STORE OPERATIONS OF 2D ARRAYS IN A SINGLE CYCLE...
- Publication number 20230045443
- Publication date Feb 9, 2023
- NVIDIA Corporation
- Ching-Yu Hung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BUILT-IN SELF-TEST FOR A PROGRAMMABLE VISION ACCELERATOR OF A SYSTE...
- Publication number 20230037738
- Publication date Feb 9, 2023
- NVIDIA Corporation
- Ahmad Itani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OFFLOADING PROCESSING TASKS TO DECOUPLED ACCELERATORS FOR INCREASIN...
- Publication number 20230042858
- Publication date Feb 9, 2023
- NVIDIA Corporation
- Ravi P. Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USING A HARDWARE SEQUENCER IN A DIRECT MEMORY ACCESS SYSTEM OF A SY...
- Publication number 20230042226
- Publication date Feb 9, 2023
- NVIDIA Corporation
- Ahmad Itani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Programmable Vision Accelerator
- Publication number 20160321074
- Publication date Nov 3, 2016
- NVIDIA Corporation
- Ching Y. HUNG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MIDDLEWARE FOR MULTIPROCESSOR SOFTWARE TESTING
- Publication number 20140040665
- Publication date Feb 6, 2014
- Manish K. Aggarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADAPTIVE ENCODING AND DECODING FOR ERROR PROTECTED PACKET-BASED FRAMES
- Publication number 20130007567
- Publication date Jan 3, 2013
- Ravi Kumar Singh
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Aligning instructions using a variable width instruction alignment...
- Publication number 20060149928
- Publication date Jul 6, 2006
- Intel Corporation, a Delaware corporation
- Thomas Tomazin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Early exception detection
- Publication number 20050223205
- Publication date Oct 6, 2005
- Juan G. Revilla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and apparatus for setting up hardware loops in a deeply pip...
- Publication number 20050102659
- Publication date May 12, 2005
- Ravi Pratap Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and apparatus for instruction alignment
- Publication number 20040236926
- Publication date Nov 25, 2004
- Analog Devices, Inc.
- Thang M. Tran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Valid bit generation and tracking in a pipelined processor
- Publication number 20040210744
- Publication date Oct 21, 2004
- Intel Corporation, a Delaware corporation
- Charles P. Roth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for branch prediction based on branch targets
- Publication number 20040186985
- Publication date Sep 23, 2004
- Analog Devices, Inc.
- Thang M. Tran
- G06 - COMPUTING CALCULATING COUNTING

Ravi Kumar Singh

Person

Patents Grantslast 30 patents

Using a hardware sequencer in a direct memory access system of a sy...

Performing load and permute with a single instruction in a system o...

Performing load and store operations of 2D arrays in a single cycle...

Using per memory bank load caches for reducing power use in a syste...

Built-in self-test for a programmable vision accelerator of a syste...

Reduced memory write requirements in a system on a chip using autom...

Hardware accelerated anomaly detection using a min/max collector in...

Using a vector processor to configure a direct memory access system...

Accelerating table lookups using a decoupled lookup table accelerat...

Performing multiple point table lookups in a single cycle in a syst...

Hardware accelerated anomaly detection using a min/max collector in...

Programmable vision accelerator

Using a hardware sequencer in a direct memory access system of a sy...

Using per memory bank load caches for reducing power use in a syste...

Using a vector processor to configure a direct memory access system...

Built-in self-test for a programmable vision accelerator of a syste...

Middleware for multiprocessor software testing

Adaptive encoding and decoding for error protected packet-based frames

Multi-cycle instructions

Efficient emulation instruction dispatch based on instruction width

Variable width alignment engine for aligning instructions based on...

Early exception detection

Method and apparatus for branch prediction based on branch targets...

Data synchronization for a test access port

FIFO write/LIFO read trace buffer with software and hardware loop c...

Methods and apparatus for instruction alignment including current i...

Aligning instructions using a variable width alignment engine havin...

Decode and dispatch of multi-issue and multiple width instructions

Hardware loops and pipeline system using advanced generation of loo...

Self-nesting interrupts

Patents Applicationslast 30 patents

USING A HARDWARE SEQUENCER IN A DIRECT MEMORY ACCESS SYSTEM OF A SY...

USING A VECTOR PROCESSOR TO CONFIGURE A DIRECT MEMORY ACCESS SYSTEM...

ACCELERATING TABLE LOOKUPS USING A DECOUPLED LOOKUP TABLE ACCELERAT...

USING A VECTOR PROCESSOR TO CONFIGURE A DIRECT MEMORY ACCESS SYSTEM...

HARDWARE ACCELERATED ANOMALY DETECTION IN A SYSTEM ON A CHIP

HYBRID SOLUTION FOR STEREO IMAGING

BUILT-IN SELF-TEST FOR A PROGRAMMABLE VISION ACCELERATOR OF A SYSTE...

USING PER MEMORY BANK LOAD CACHES FOR REDUCING POWER USE IN A SYSTE...

USING A HARDWARE SEQUENCER IN A DIRECT MEMORY ACCESS SYSTEM OF A SY...

PERFORMING LOAD AND PERMUTE WITH A SINGLE INSTRUCTION IN A SYSTEM O...

USING A VECTOR PROCESSOR TO CONFIGURE A DIRECT MEMORY ACCESS SYSTEM...

SIMD DATA PATH ORGANIZATION TO INCREASE PROCESSING THROUGHPUT IN A...

ACCELERATING TABLE LOOKUPS USING A DECOUPLED LOOKUP TABLE ACCELERAT...

PERFORMING MULTIPLE POINT TABLE LOOKUPS IN A SINGLE CYCLE IN A SYST...

HARDWARE ACCELERATED ANOMALY DETECTION IN A SYSTEM ON A CHIP

USING PER MEMORY BANK LOAD CACHES FOR REDUCING POWER USE IN A SYSTE...

REDUCED MEMORY WRITE REQUIREMENTS IN A SYSTEM ON A CHIP USING AUTOM...

PERFORMING LOAD AND STORE OPERATIONS OF 2D ARRAYS IN A SINGLE CYCLE...

BUILT-IN SELF-TEST FOR A PROGRAMMABLE VISION ACCELERATOR OF A SYSTE...

OFFLOADING PROCESSING TASKS TO DECOUPLED ACCELERATORS FOR INCREASIN...

USING A HARDWARE SEQUENCER IN A DIRECT MEMORY ACCESS SYSTEM OF A SY...

Programmable Vision Accelerator

MIDDLEWARE FOR MULTIPROCESSOR SOFTWARE TESTING

ADAPTIVE ENCODING AND DECODING FOR ERROR PROTECTED PACKET-BASED FRAMES

Aligning instructions using a variable width instruction alignment...

Early exception detection

Methods and apparatus for setting up hardware loops in a deeply pip...

Methods and apparatus for instruction alignment

Valid bit generation and tracking in a pipelined processor

Method and apparatus for branch prediction based on branch targets