Ravi Sundaresan

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
CMOS integrated circuit device with LDD n-channel transistor and no...
- Patent number 6,759,717
- Issue date Jul 6, 2004
- STMicroelectronics, Inc.
- Pervez Hassan Sagarwala
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to form a self-aligned CMOS inverter using vertical device i...
- Patent number 6,747,314
- Issue date Jun 8, 2004
- Chartered Semiconductor Manufacturing Ltd.
- Ravi Sundaresan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming variable-K gate dielectric
- Patent number 6,709,934
- Issue date Mar 23, 2004
- Chartered Semiconductor Manufacturing Ltd.
- James Yong Meng Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to form a vertical transistor by first forming a gate/spacer...
- Patent number 6,544,824
- Issue date Apr 8, 2003
- Chartered Semiconductor Manufacturing Ltd.
- Yelehanka Pradeep
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to form self-aligned source/drain CMOS device on insulated s...
- Patent number 6,541,327
- Issue date Apr 1, 2003
- Chartered Semiconductor Manufacturing Ltd.
- Lap Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to form and/or isolate vertical transistors
- Patent number 6,511,884
- Issue date Jan 28, 2003
- Chartered Semiconductor Manufacturing Ltd.
- Elgin Quek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of patterning gate electrode with ultra-thin gate dielectric
- Patent number 6,475,916
- Issue date Nov 5, 2002
- Chartered Semiconductor Manufacturing Ltd.
- James Yong Meng Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to form an air-gap under the edges of a gate electrode by us...
- Patent number 6,468,877
- Issue date Oct 22, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Yelehanka Ramachandramurthy Pradeep
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to form a self-aligned CMOS inverter using vertical device i...
- Patent number 6,461,900
- Issue date Oct 8, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Ravi Sundaresan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to form an inverted staircase STI structure by etch-depositi...
- Patent number 6,461,887
- Issue date Oct 8, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Yelehanka Ramachandramurthy Pradeep
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to form very high mobility vertical channel transistor by se...
- Patent number 6,455,377
- Issue date Sep 24, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Jia Zhen Zheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to form a vertical transistor by selective epitaxial growth...
- Patent number 6,440,800
- Issue date Aug 27, 2002
- Chartered Semiconductor Manufacturing Ltd.
- James Yong Meng Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to control the channel length of a vertical transistor by fi...
- Patent number 6,436,770
- Issue date Aug 20, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Ying Keung Leung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming variable-K gate dielectric
- Patent number 6,436,774
- Issue date Aug 20, 2002
- Chartered Semiconductor Manufacturing Ltd.
- James Yong Meng Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating a self aligned S/D CMOS device on insulated...
- Patent number 6,417,054
- Issue date Jul 9, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Jia Zhen Zheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to form low-overlap-capacitance transistors by forming micro...
- Patent number 6,417,056
- Issue date Jul 9, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Elgin Quek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a transistor gate dielectric with high-K and low...
- Patent number 6,406,945
- Issue date Jun 18, 2002
- Chartered Semiconductor Manufacturing Ltd.
- James Yong Meng Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to form a low parasitic capacitance pseudo-SOI CMOS device
- Patent number 6,403,485
- Issue date Jun 11, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Elgin Quek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to form a recessed source drain on a trench side wall with a...
- Patent number 6,380,088
- Issue date Apr 30, 2002
- Chartered Semiconductor Manufacturing, Inc.
- Lap Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selective formation of hydrogen rich PECVD silicon nitride for impr...
- Patent number 6,372,569
- Issue date Apr 16, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Yong Meng Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to form a balloon shaped STI using a micro machining techniq...
- Patent number 6,313,008
- Issue date Nov 6, 2001
- Chartered Semiconductor Manufacturing Inc.
- Ying Keung Leung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to form an elevated S/D CMOS device by contacting S/D throug...
- Patent number 6,306,714
- Issue date Oct 23, 2001
- Chartered Semiconductor Manufacturing Inc.
- Yang Pan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to form smaller channel with CMOS device by isotropic etchin...
- Patent number 6,306,715
- Issue date Oct 23, 2001
- Chartered Semiconductor Manufacturing Ltd.
- Lap Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to form self-aligned elevated source/drain by selective remo...
- Patent number 6,303,449
- Issue date Oct 16, 2001
- Chartered Semiconductor Manufacturing Inc.
- Yang Pan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to form transistors with multiple threshold voltages (VT) us...
- Patent number 6,300,177
- Issue date Oct 9, 2001
- Chartered Semiconductor Manufacturing Inc.
- Ravi Sundaresan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming contact to polysilicon gate for MOS devices
- Patent number 6,261,935
- Issue date Jul 17, 2001
- Chartered Semiconductor Manufacturing Ltd.
- Alex See
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating a CMOS integrated circuit device with LDD N-c...
- Patent number 6,221,709
- Issue date Apr 24, 2001
- STMicroelectronics, Inc.
- Pervez Hassan Sagarwala
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Method to form a self-aligned CMOS inverter using vertical device i...
- Publication number 20030075758
- Publication date Apr 24, 2003
- Chartered Semiconductor Manufacturing Ltd.
- Ravi Sundaresan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method to improve latchup by forming selective sloped staircase STI...
- Publication number 20030017710
- Publication date Jan 23, 2003
- Chartered Semiconductor Manufacturing Ltd.
- Pan Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for forming variable-K gate dielectric
- Publication number 20020173106
- Publication date Nov 21, 2002
- Chartered Semiconductor Manufacturing Ltd.
- James Yong Meng Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FABRICATING A SELF ALIGNED S/D CMOS DEVICE ON INSULATED...
- Publication number 20020102798
- Publication date Aug 1, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Jia Zhen Zheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for forming variable-K gate dielectric
- Publication number 20020100947
- Publication date Aug 1, 2002
- Chartered Semiconductor Manufacturing Inc.
- James Yong Meng Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method to form a vertical transistor by selective epitaxial growth...
- Publication number 20020102784
- Publication date Aug 1, 2002
- Chartered Semiconductor Manufacturing Ltd.
- James Yong Meng Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method to form very high mobility vertical channel transistor by se...
- Publication number 20020098655
- Publication date Jul 25, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Jia Zhen Zheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CMOS integrated circuit device with LDD n-channel transistor and no...
- Publication number 20010009796
- Publication date Jul 26, 2001
- Pervez Hassan Sagarwala
- H01 - BASIC ELECTRIC ELEMENTS

Ravi Sundaresan

Person

Patents Grantslast 30 patents

CMOS integrated circuit device with LDD n-channel transistor and no...

Method to form a self-aligned CMOS inverter using vertical device i...

Method for forming variable-K gate dielectric

Method to form a vertical transistor by first forming a gate/spacer...

Method to form self-aligned source/drain CMOS device on insulated s...

Method to form and/or isolate vertical transistors

Method of patterning gate electrode with ultra-thin gate dielectric

Method to form an air-gap under the edges of a gate electrode by us...

Method to form a self-aligned CMOS inverter using vertical device i...

Method to form an inverted staircase STI structure by etch-depositi...

Method to form very high mobility vertical channel transistor by se...

Method to form a vertical transistor by selective epitaxial growth...

Method to control the channel length of a vertical transistor by fi...

Method for forming variable-K gate dielectric

Method for fabricating a self aligned S/D CMOS device on insulated...

Method to form low-overlap-capacitance transistors by forming micro...

Method for forming a transistor gate dielectric with high-K and low...

Method to form a low parasitic capacitance pseudo-SOI CMOS device

Method to form a recessed source drain on a trench side wall with a...

Selective formation of hydrogen rich PECVD silicon nitride for impr...

Method to form a balloon shaped STI using a micro machining techniq...

Method to form an elevated S/D CMOS device by contacting S/D throug...

Method to form smaller channel with CMOS device by isotropic etchin...

Method to form self-aligned elevated source/drain by selective remo...

Method to form transistors with multiple threshold voltages (VT) us...

Method of forming contact to polysilicon gate for MOS devices

Method of fabricating a CMOS integrated circuit device with LDD N-c...

Patents Applicationslast 30 patents

Method to form a self-aligned CMOS inverter using vertical device i...

Method to improve latchup by forming selective sloped staircase STI...

Method for forming variable-K gate dielectric

METHOD FOR FABRICATING A SELF ALIGNED S/D CMOS DEVICE ON INSULATED...

Method for forming variable-K gate dielectric

Method to form a vertical transistor by selective epitaxial growth...

Method to form very high mobility vertical channel transistor by se...

CMOS integrated circuit device with LDD n-channel transistor and no...